Reset and clock control (RCC) RM0367
214/1043 RM0367 Rev 7
7.3.18 APB2 peripheral clock enable in Sleep mode
register (RCC_APB2SMENR)
Address: 0x44
Reset value: the bits corresponding to the available peripherals are set.
Access: no wait state, word, half-word and byte access
Bit 8 MIFSMEN: NVM interface clock enable during Sleep mode bit
This bit is set and reset by software.
0: NVM interface clock disabled in Sleep mode
1: NVM interface clock enabled in Sleep mode
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 DMASMEN: DMA clock enable during Sleep mode bit
This bit is set and reset by software.
0: DMA clock disabled in Sleep mode
1: DMA clock enabled in Sleep mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG
SMEN
Res. Res. Res. Res. Res. Res.
rw
1514131211109 8 7 6 543210
Res.
USART1
SMEN
Res.
SPI1
SMEN
Res. Res.
ADC
SMEN
Res. Res. Res.
TIM22
SMEN
Res. Res.
TIM21
SMEN
Res.
SYSCF
SMEN
rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DBGSMEN: DBG clock enable during Sleep mode bit
This bit is set and cleared by software.
0: DBG clock disabled in Sleep mode
1: DBG clock enabled in Sleep mode (if enabled by DBGEN)
Bits 21:15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: USART1 clock disabled in Sleep mode
1: USART1 clock enabled in Sleep mode (if enabled by USART1EN)
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: SPI1 clock disabled in Sleep mode
1: SPI1 clock enabled in Sleep mode (if enabled by SPI1EN)
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 ADCSMEN: ADC clock enable during Sleep mode bit
This bit is set and cleared by software.
0: ADC clock disabled in Sleep mode
1: ADC clock enabled in Sleep mode (if enabled by ADCEN)
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