Power control (PWR) RM0367
152/1043 RM0367 Rev 7
generated when V
DD
drops below the PVD threshold. As an example the service routine
could perform emergency shutdown tasks.
Figure 15. PVD thresholds
6.2.4 Internal voltage reference (V
REFINT
)
The internal reference (V
REFINT
) provides stable voltage for analog peripherals. The
functions managed through the internal voltage reference (V
REFINT
) are BOR, PVD, ADC,
HSI48, LCD and comparators. The internal voltage reference (V
REFINT
) is always enabled
when one of these features is used.
The internal voltage reference consumption is not negligible, in particular in Stop and
Standby mode. To reduce power consumption, the ULP bit (ultra-low-power) in the
PWR_CR register can be set to disable the internal voltage reference. However, in this
case, when exiting from the Stop/Standby mode, the functions managed through the internal
voltage reference are not reliable during the internal voltage reference startup time (up to
3ms).
To reduce the wakeup time, the device can exit from Stop/Standby mode without waiting for
the internal voltage reference startup time. This is performed by setting the FWU bit (Fast
wakeup) in the PWR_CR register before entering Stop/Standby mode.
If the ULP bit is set, the functions that were enabled before entering Stop/Standby mode will
be disabled during these modes, and enabled again only after the end of the internal voltage
reference startup time whatever FWU value. The VREFINTRDYF flag in the PWR_CSR
register indicates that the internal voltage reference is ready.
When the device exits from low-power mode on an NRST pulse, it does not wait for internal
voltage reference startup (even if ULP=1 and FWU=0). The application should check the
VREFINTRDYF flag if necessary.
Note: When the LCD is active (LCDEN bit of LCD_CR set), VREFINT is required. ULP bit must
consequently be reset.
MSv32795V2
VDD/VDDA
PVD output
PVD threshold
100mV
hysteresis
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