RM0367 Rev 7 643/1043
RM0367 Independent watchdog (IWDG)
644
25.4.5 IWDG window register (IWDG_WINR)
Address offset: 0x10
Reset value: 0x0000 0FFF (reset by Standby mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. WIN[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 WIN[11:0]: Watchdog counter window value
These bits are write access protected, see Section 25.3.4, they contain the high limit of the
window value to be compared with the downcounter.
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x0
The WVU bit in the IWDG status register (IWDG_SR) must be reset in order to be able to
change the reload value.
Note: Reading this register returns the reload value from the V
DD
voltage domain. This value
may not be valid if a write operation to this register is ongoing. For this reason the value
read from this register is valid only when the WVU bit in the IWDG status register
(IWDG_SR) is reset.
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