Independent watchdog (IWDG) RM0367
636/1043 RM0367 Rev 7
25 Independent watchdog (IWDG)
25.1 Introduction
The devices feature an embedded watchdog peripheral that offers a combination of high
safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral
detects and solves malfunctions due to software failure, and triggers system reset when the
counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI)
and thus stays active even if the main clock fails.
The IWDG is best suited for applications that require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. For further information on the window watchdog, refer to Section 26 on page
645.
25.2 IWDG main features
• Free-running downcounter
• Clocked from an independent RC oscillator (can operate in Standby and Stop modes)
• Conditional reset
– Reset (if watchdog activated) when the downcounter value becomes lower than
0x000
– Reset (if watchdog activated) if the downcounter is reloaded outside the window
25.3 IWDG functional description
25.3.1 IWDG block diagram
Figure 207 shows the functional blocks of the independent watchdog module.
Figure 207. Independent watchdog block diagram
1. The register interface is located in the CORE voltage domain. The watchdog function is located in the V
DD
voltage domain, still functional in Stop and Standby modes.
IWDG reset
prescaler
IWDG_PR
Prescaler register
IWDG_RLR
Reload register
8-bit
LSI
(40 kHz)
IWDG_KR
Key register
CORE
VDD voltage domain
IWDG_SR
Status register
MS19944V2
12-bit reload value
12-bit downcounter
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