EasyManuals Logo

ST STM32L0x3 User Manual

ST STM32L0x3
1043 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #623 background image
RM0367 Rev 7 623/1043
RM0367 Low-power timer (LPTIM)
635
counter comparator. Within this latency period, any additional write into these registers must
be avoided.
The ARROK flag and the CMPOK flag in the LPTIM_ISR register indicate when the write
operation is completed to respectively the LPTIM_ARR register and the LPTIM_CMP
register.
After a write to the LPTIM_ARR register or the LPTIM_CMP register, a new write operation
to the same register can only be performed when the previous write operation is completed.
Any successive write before respectively the ARROK flag or the CMPOK flag be set, will
lead to unpredictable results.
24.4.11 Counter mode
The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be
used to count internal clock cycles. The CKSEL and COUNTMODE bits control which
source will be used for updating the counter.
In case the LPTIM is configured to count external events on Input1, the counter can be
updated following a rising edge, falling edge or both edges depending on the value written
to the CKPOL[1:0] bits.
The count modes below can be selected, depending on CKSEL and COUNTMODE values:
CKSEL = 0: the LPTIM is clocked by an internal clock source
COUNTMODE = 0
The LPTIM is configured to be clocked by an internal clock source and the LPTIM
counter is configured to be updated following each internal clock pulse.
COUNTMODE = 1
The LPTIM external Input1 is sampled with the internal clock provided to the
LPTIM.
Consequently, in order not to miss any event, the frequency of the changes on the
external Input1 signal should never exceed the frequency of the internal clock
provided to the LPTIM. Also, the internal clock provided to the LPTIM must not be
prescaled (PRESC[2:0] = 000).
CKSEL = 1: the LPTIM is clocked by an external clock source
COUNTMODE value is don’t care.
In this configuration, the LPTIM has no need for an internal clock source (except if the
glitch filters are enabled). The signal injected on the LPTIM external Input1 is used as
system clock for the LPTIM. This configuration is suitable for operation modes where
no embedded oscillator is enabled.
For this configuration, the LPTIM counter can be updated either on rising edges or
falling edges of the input1 clock signal but not on both rising and falling edges.
Since the signal injected on the LPTIM external Input1 is also used to clock the LPTIM
kernel logic, there is some initial latency (after the LPTIM is enabled) before the counter
is incremented. More precisely, the first five active edges on the LPTIM external Input1
(after LPTIM is enable) are lost.
For code example, refer to A.12.1: Pulse counter configuration code example.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM32L0x3 and is the answer not in the manual?

ST STM32L0x3 Specifications

General IconGeneral
BrandST
ModelSTM32L0x3
CategoryMicrocontrollers
LanguageEnglish

Related product manuals