RM0367 Rev 7 399/1043
RM0367 Liquid crystal display controller (LCD)
413
17.4.6 Double buffer memory
Using its double buffer memory the LCD controller ensures the coherency of the displayed
information without having to use interrupts to control LCD_RAM modification.
The application software can access the first buffer level (LCD_RAM) through the APB
interface. Once it has modified the LCD_RAM, it sets the UDR flag in the LCD_SR register.
This UDR flag (update display request) requests the updated information to be moved into
the second buffer level (LCD_DISPLAY).
This operation is done synchronously with the frame (at the beginning of the next frame),
until the update is completed, the LCD_RAM is write protected and the UDR flag stays high.
Once the update is completed another flag (UDD - Update Display Done) is set and
generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one even
frame.
The update will not occur (UDR = 1 and UDD = 0) until the display is enabled (LCDEN = 1)
17.4.7 COM and SEG multiplexing
Output pins versus duty modes
The output pins consists of up to:
• SEG[51:0]
• COM[3:0]
Depending on the duty configuration, the COM and SEG output pins may have different
functions:
• In static, 1/2, 1/3 and 1/4 duty modes there are up to 52 SEG pins and respectively 1, 2,
3 and 4 COM pins
• In 1/8 duty mode (DUTY[2:0] = 100), COM[7:4] outputs are available on the
SEG[51:48] and SEG[31:28] pins on category 5 and category 3 devices, respectively.
This allows reducing the number of available segments.
Remapping capability for small packages
Additionally, it is possible to remap 4 segments by setting the MUX_SEG bit in the LCD_CR
register. This is particularly useful when using smaller device types with fewer external pins.
When MUX_SEG is set, output pins SEG[51:48] have the same function as SEG[31:28].
This feature is available only on category 5 devices.
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