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RM0367 Rev 7 591/1043

RM0367 General-purpose timers (TIM21/22)

601

22.4.6 TIM21/22 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. TG Res. Res. Res. CC2G CC1G UG

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Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TG: Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by

hardware.

0: No action

1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled

Bits 5:3 Reserved, must be kept at reset value.

Bit 2 CC2G: Capture/compare 2 generation

refer to CC1G description

Bit 1 CC1G: Capture/compare 1 generation

This bit is set by software to generate an event, it is automatically cleared by hardware.

0: No action

1: A capture/compare event is generated on channel 1:

If channel CC1 is configured as output:

the CC1IF flag is set, the corresponding interrupt is sent if enabled.

If channel CC1 is configured as input:

The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the

corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was

already high.

Bit 0 UG: Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Re-initializes the counter and generates an update of the registers. The prescaler counter

is also cleared and the prescaler ratio is not affected. The counter is cleared.

ST STM32L0x3 User Manual

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