Clock recovery system (CRS) RM0367
228/1043 RM0367 Rev 7
8.4.3 Frequency error measurement
The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD
value on each SYNC event. It starts counting down till it reaches the zero value, where the
ESYNC (expected synchronization) event is generated. Then it starts counting up to the
OUTRANGE limit where it eventually stops (if no SYNC event is received) and generates a
SYNCMISS event. The OUTRANGE limit is defined as the frequency error limit (FELIM field
of the CRS_CFGR register) multiplied by 128.
When the SYNC event is detected, the actual value of the frequency error counter and its
counting direction are stored in the FECAP (frequency error capture) field and in the FEDIR
(frequency error direction) bit of the CRS_ISR register. When the SYNC event is detected
during the downcounting phase (before reaching the zero value), it means that the actual
frequency is lower than the target (and so, that the TRIM value must be incremented), while
when it is detected during the upcounting phase it means that the actual frequency is higher
(and that the TRIM value must be decremented).
Figure 20. CRS counter behavior
CRS counter value
RELOAD
OUTRANGE
(128 x FELIM)
WARNING LIMIT
(3 x FELIM)
TOLERANCE LIMIT
(FELIM)
SYNCERR
SYNCWARN
SYNCOK
SYNCWARN
SYNCMISS
+2
+1
0
-1
-2
0
Down
Up
Frequency
error counter
stopped
0
Trimming action:
CRS event:
MSv32122V1
ESYNC
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