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Extended interrupt and event controller (EXTI) RM0367

298/1043 RM0367 Rev 7

13.5.3 EXTI rising edge trigger selection register (EXTI_RTSR)

Address offset: 0x08

Reset value: 0x0000 0000

Note: The configurable wakeup lines are edge triggered, no glitch must be generated on these

lines.

If a rising edge on the configurable interrupt line occurs while writing to the EXTI_RTSR

Rising and falling edge triggers can be set for the same interrupt line. In this configuration,

both generate a trigger condition.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 EMx: Event mask on line x (x = 29 to 28)

0: Event request from Line x is masked

1: Event request from Line x is not masked

Bit 27 Reserved, must be kept at reset value.

Bits 26:19 EMx: Event mask on line x (x = 26 to 19)

0: Event request from Line x is masked

1: Event request from Line x is not masked

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 EMx: Event mask on line x (x = 17 to 0)

0: Event request from Line x is masked

1: Event request from Line x is not masked

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 Res. RT17 RT16

rw rw rw rw rw rw

1514131211109 8 7654RT1621 0

RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:19 RTx: Rising trigger event configuration bit of line x (x = 22 to 19)

0: Rising trigger disabled (for Event and Interrupt) for input line x

1: Rising trigger enabled (for Event and Interrupt) for input line x

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 RTx: Rising trigger event configuration bit of line x (x = 17 to 0)

0: Rising trigger disabled (for Event and Interrupt) for input line x

1: Rising trigger enabled (for Event and Interrupt) for input line x

ST STM32L0x3 User Manual

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