Liquid crystal display controller (LCD) RM0367
398/1043 RM0367 Rev 7
External decoupling
Devices with V
LCD
rails decoupling capability (see device datasheets) allow adding
decoupling capacitors on the VLCD intermediate voltage rails that available on
LCD_VLCD1, LCD_VLCD2 and LCD_VLCD3 for stabilization purpose (see Figure 75).
Spikes might be observed when the voltage applied to the pixel is alternating. In this case,
these decoupling capacitors will help to get a steady voltage resulting in a higher contrast.
This capability is particularly useful for consumption reason as it allow to select lower
PON[2:0] values in the LCD_FCR register.
To connect the V
LCD
rails as described in Table 76 to the dedicated GPIOs, configure the
LCD_CAPA[4:0] bits of the SYSCFG_CFGR2 register (see Section 10.2.2: SYSCFG
peripheral mode configuration register (SYSCFG_CFGR2).
In order to be effective, the values of these decoupling capacitors must be tuned according
to the LCD glass and the PCB capacitances. As a guideline the user can set the decoupling
capacitor values to approximately 10 times the LCD capacitance.
Deadtime
In addition to using the CC[2:0] bits, the contrast can be controlled by programming a dead
time between each frame. During the dead time the COM and SEG values are put to V
SS
.
The DEAD[2:0] bits in the LCD_FCR register can be used to program a time of up to eight
phase periods. This dead time reduces the contrast without modifying the frame rate.
Figure 76. Deadtime
Table 76. VLCDrail connections to GPIO pins
Bias
Pin
(selected by LCD_CAPA[4:0] bits)
1/2 1/3 1/4
VLCDrail3 Not used Not used 3/4 V
LCD
PB0 or PE12
VLCDrail2 1/2 V
LCD
2/3 V
LCD
1/2 V
LCD
PB2
VLCDrail1 Not used 1/3 V
LCD
1/4 V
LCD
PB12 or PE11
MS33448V1
odd frame even frame odd frame even framedead time
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