ST STM32L0x3 User Manual

RM0367 Rev 7 455/1043
RM0367 AES hardware accelerator (AES)
466
word to be read from the AES_DOUTR register. It asserts four DMA requests to transfer one
128-bit (four-word) output data block to memory, as shown in Figure 102.
See Table 91 for recommended DMA configuration.
Figure 102. DMA transfer of a 128-bit data block during output phase
DMA operation in different operating modes
DMA operations are usable when Mode 1 (encryption) or Mode 3 (decryption) are selected
via the MODE[1:0] bitfield of the register AES_CR. As in Mode 2 (key derivation) the
AES_KEYRx registers must be written by software, enabling the DMA transfer through the
DMAINEN and DMAOUTEN bits of the AES_CR register have no effect in that mode.
Table 91. DMA channel configuration for AES-to-memory data transfer
DMA channel control
register field
Recommended configuration
Transfer size
It is the message length multiple of AES block size (4 words). According to
the case extra bytes will have to be discarded.
Source burst size
(peripheral)
Single
Destination burst size
(memory)
Single
DMA FIFIO size AES FIFO_size = 4 bytes
Source transfer width
(peripheral)
32-bit words
Destination transfer
width (memory)
32-bit words
Source address
increment (peripheral)
Fixed address of AES_DINR (no increment)
Destination address
increment (memory)
Yes, after each 32-bit transfer
MSv42161V1
AES core output buffer
LSB
MSB
(No swapping)
Memory accessed through DMA
Word2Word3 Word0Word1
DMA
single read
DMA req N DMA req N+1 DMA req N+2 DMA req N+3
O127 O96
O63 O32
O31 O0
O64O95
D127 D96
D63 D32
D31 D0
D64D95
DOUT[127:96] DOUT[95:64] DOUT[63:32] DOUT[31:0]
DMA
single read
DMA
single read
DMA
single read
Chronological order
Increasing address
LSBMSB
System
AES
peripheral
1 2 3 4
1 2 3 4
1
Order of read from AES_DOUTR
4
AES_DOUTR

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English