RM0367 Rev 7 379/1043
RM0367 Comparator (COMP)
383
16.3.3 COMP reset and clocks
The COMP clock provided by the clock controller is synchronous with the PCLK (APB
clock).
There is no clock enable control bit provided in the RCC controller. Reset and clock enable
bits are common for COMP and SYSCFG.
Important: The polarity selection logic and the output redirection to the port works
independently from the PCLK clock. This allows the comparator to work even in Stop mode.
16.3.4 Comparator LOCK mechanism
The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications having specific functional safety requirements, it is necessary to
insure that the comparator programming cannot be altered in case of spurious register
access or program counter corruption.
For this purpose, the comparator control and status registers can be write-protected (read-
only).
Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the
whole COMPx_CSR register to become read-only, including the COMPx LOCK bit.
The write protection can only be reset by a MCU reset.
16.3.5 Power mode
COMP2 power consumption versus propagation delay can be adjusted to have the optimum
trade-off for a given application.
COMP2_SPEED bit in the COMP2_CSR register can be programmed to provide either
higher speed/consumption or lower speed/consumption.
16.4 COMP interrupts
The comparator outputs are internally connected to the Extended interrupts and events
controller. Each comparator has its own EXTI line and can generate either interrupts or
events. The same mechanism is used to exit from low-power modes.
Refer to Interrupt and events section for more details.
16.5 COMP registers
16.5.1 Comparator 1 control and status register (COMP1_CSR)
The COMP1_CSR is the Comparator1 control/status register. It contains all the bits /flags
related to comparator1.
Address offset: 0x18
System reset value: 0x0000 0000
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