RM0367 Rev 7 259/1043
RM0367 System configuration controller (SYSCFG)
264
10.2.3 Reference control and status register (SYSCFG_CFGR3)
The SYSCFG_CFGR3 register is the reference control/status register. It contains all the
bits/flags related to VREFINT and temperature sensor.
Address offset: 0x20
System reset value: 0x0000 0000
Bits 7:4 Reserved, must be kept at reset value
Bits 5:1 LCD_CAPA[4:0]: Decoupling capacitance connection (refer to the datasheet for details on
the device capability)
These bits are set and cleared by software. They control the connection of the internal V
LCD
rails supply voltage to a dedicated I/O (LCD_VLCD1, LCD_VLCD2, LCD_VLCD3) to
perform an optional decoupling.
Bit 1 controls the connection of VLCDrail1 on PB2/LCD_VLCD1
0: VLCDrail2 not connected to PB2/LCD_VLCD1
1: VLCDrail2 connected to PB2/LCD_VLCD1
Bit 2 controls the connection of VLCDrail1 on PB12
Bit 3 controls the connection of VLCDrail3 on PB0
Bit 4 controls the connection of VLCDrail1 on PE11
Bit 5 controls the connection of VLCDrail3 on PE12
Refers to Section : External decoupling for details.
Bit 0 FWDIS: Firewall disable bit
This bit is set by default (after reset). It is cleared by software to protect the access to the
memory segments according to the Firewall configuration.Once cleared it cannot be set by
software. Only a system reset set the bit.
0: Firewall access enabled
1: Firewall access disabled
Note: This bit cannot be set by an APB reset. A system reset is required to set it.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REF_
LOCK
VREFINT
_RDYF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rs r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res.
ENREF_
HSI48
ENBUF_
VREFINT_
COMP2
Res. Res.
ENBUF_
SENSOR
_ADC
ENBUF_
VREFINT
_ ADC
Res. Res.
SEL_VREF
_OUT
Res. Res. Res.
EN_VR
EFINT
rw rw rw rw rw rw rw
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