System configuration controller (SYSCFG) RM0367
260/1043 RM0367 Rev 7
Bit 31 REF_LOCK: SYSCFG_CFGR3 lock bit
This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the reference control/Status register, SYSCFG_CFGR3[31:0].
0: SYSCFG_CFGR3[31:0] bits are read/write
1: SYSCFG_CFGR3[31:0] bits are read-only
Bit 30 VREFINT_RDYF: VREFINT ready flag
This bit is read-only. It shows the state of the internal voltage reference, VREFINT. When
set, it indicates that VREFINT is available for BOR, PVD and LCD.
0: VREFINT OFF
1: VREFINT ready
Bits 29:14 Reserved, must be kept at reset value
Bit 13 ENREF_HSI48: VREFINT reference for HSI48 oscillator enable bit
This bit is set and cleared by software (only if REF_LOCK not set).
0: Buffer used to generate VREFINT reference for the HSI48 oscillator switched OFF.
1: Buffer used to generate VREFINT reference for the HSI48oscillator switched ON.
Bit 12 ENBUF_VREFINT_COMP2: VREFINT reference for COMP2 scaler enable bit
This bit is set and cleared by software (only if REF_LOCK not set).
0: Disables the buffer used to generate VREFINT references for COMP2.
1: Enables the buffer used to generate VREFINT references for COMP2.
Bits 11:10 Reserved, must be kept at reset value
Bit 9 ENBUF_SENSOR_ADC: Temperature sensor reference for ADC enable bit
This bit is set and cleared by software (only if REF_LOCK not set). When this bit is set, the
VREFINT is automatically enabled.
0: Disables the buffer used to generate VREFINT reference for the temperature sensor.
1: Enables the buffer used to generate VREFINT reference for the temperature sensor.
Bit 8 ENBUF_VREFINT_ADC: VREFINT reference for ADC enable bit
This bit is set and cleared by software (only if REF_LOCK not set).
0: Disables the buffer used to generate VREFINT reference for the ADC.
1: Enables the buffer used to generate VREFINT reference for the ADC.
Bits 7:6 Reserved, must be kept at reset value
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