ST STM32L0x3 User Manual

General-purpose timers (TIM2/TIM3) RM0367
538/1043 RM0367 Rev 7
Note: The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
21.4.10 TIMx counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
21.4.11 TIMx prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
21.4.12 TIMx auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF FFFF
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CNT[15:0]
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Bits 15:0 CNT[15:0]: Low counter value
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PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
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ARR[15:0]
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Bits 15:0 ARR[15:0]: Low Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 21.3.1: Time-base unit on page 481 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English