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RM0367 Rev 7 323/1043

RM0367 Analog-to-digital converter (ADC)

352

converted data from the ADC_DR register to the destination location selected by the

software.

Note: The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.

Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA

transfer request in time, the ADC stops generating DMA requests and the data

corresponding to the new conversion is not transferred by the DMA. Which means that all

the data transferred to the RAM can be considered as valid.

Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten

(refer to Section 14.5.2: ADC overrun (OVR, OVRMOD) on page 321).

The DMA transfer requests are blocked until the software clears the OVR bit.

Two different DMA modes are proposed depending on the application use and are

configured with bit DMACFG in the ADC_CFGR1 register:

• DMA one shot mode (DMACFG = 0).

This mode should be selected when the DMA is programmed to transfer a fixed

number of data words.

• DMA circular mode (DMACFG = 1)

This mode should be selected when programming the DMA in circular mode.

DMA one shot mode (DMACFG = 0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data

word is available and stops generating DMA requests once the DMA has reached the last

DMA transfer (when a DMA_EOT interrupt occurs, see Section 11: Direct memory access

controller (DMA) on page 265) even if a conversion has been started again.

For code example, refer to A.8.9: DMA one shot mode sequence code example.

When the DMA transfer is complete (all the transfers configured in the DMA controller have

been done):

• The content of the ADC data register is frozen.

• Any ongoing conversion is aborted and its partial result discarded

• No new DMA request is issued to the DMA controller. This avoids generating an

overrun error if there are still conversions which are started.

• The scan sequence is stopped and reset

• The DMA is stopped

DMA circular mode (DMACFG = 1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data

word is available in the data register, even if the DMA has reached the last DMA transfer.

This allows the DMA to be configured in circular mode to handle a continuous analog input

data stream.

For code example, refer to A.8.10: DMA circular mode sequence code example.

ST STM32L0x3 User Manual

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