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Analog-to-digital converter (ADC) RM0367

348/1043 RM0367 Rev 7

14.12.7 ADC watchdog threshold register (ADC_TR)

Address offset: 0x20

Reset value: 0x0FFF 0000

14.12.8 ADC channel selection register (ADC_CHSELR)

Address offset: 0x28

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. HT[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

1514131211109876543210

Res. Res. Res. Res. LT[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT[11:0]: Analog watchdog higher threshold

These bits are written by software to define the higher threshold for the analog watchdog. Refer to

Section 14.7: Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) on page 326

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no

conversion is ongoing).

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 LT[11:0]: Analog watchdog lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

Refer to Section 14.7: Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) on

page 326.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no

conversion is ongoing).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

CHSEL

rw rw rw

1514131211109876543210

CHSEL

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ST STM32L0x3 User Manual

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