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RM0367 Rev 7 355/1043

RM0367 Digital-to-analog converter (DAC)

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15.3 DAC output buffer enable

The DAC integrates two output buffers that can be used to reduce the output impedance

and to drive external loads directly without having to add an external operational amplifier.

The DAC channel output buffer can be enabled and disabled through the BOFF1 bit in the

DAC_CR register.

15.4 DAC channel enable

Each DAC channel can be powered on by setting the corresponding ENx bit in the DAC_CR

WAKEUP

Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital

interface is enabled even if the ENx bit is reset.

15.5 Single mode functional description

15.5.1 DAC data format

There are three possibilities:

• 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits

(stored into the DHRx[11:4] bits)

• 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits

(stored into the DHRx[11:0] bits)

• 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits

(stored into the DHRx[11:0] bits)

Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and

stored into the corresponding DHRx (data holding registerx, which are internal non-memory-

mapped registers). The DHRx register is then loaded into the DORx register either

automatically, by software trigger or by an external event trigger.

Figure 59. Data registers in single DAC channel mode

15.5.2 DAC channel conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must

be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx,

DAC_DHR12Rx).

Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx

31 24 15 7 0

8-bit right aligned

12-bit left aligned

12-bit right aligned

ai14710b

ST STM32L0x3 User Manual

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