ST STM32L0x3 User Manual

Low-power universal asynchronous receiver transmitter (LPUART) RM0367
850/1043 RM0367 Rev 7
Figure 273. Transmission using DMA
Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in LPUART_CR3 register.
Data is loaded from the LPUART_RDR register to a SRAM area configured using the DMA
peripheral (refer Section Direct memory access controller (DMA)) whenever a data byte is
received. To map a DMA channel for LPUART reception, use the following procedure:
1. Write the LPUART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from LPUART_RDR to this memory area after each
RXNE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.
F2 F3F1
MSv31890V2
Software
configures
DMA to send 3
data blocks
and enables
LPUART
The DMA
transfer is
complete
(TCIF=1 in
DMA_ISR)
DMA writes F2
into
LPUART_TDR
DMA writes F3
into
LPUART_TDR
Software waits until TC=1
Set by hardware
Cleared by software
Set by hardware
TX line
TXE flag
LPUART_TDR
DMA request
DMA writes
LPUART_TDR
DMA TCIF flag(transfer complete)
TC flag
Frame 1
Frame 2
Frame 3
Idle preamble
Set by hardware cleared
by DMA read
Set by hardware cleared by
DMA read
Set by hardware
Ignored by the DMA because the transfer
is complete
a
DMA writes F1
into
LPUART_TDR

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English