RM0367 Rev 7 543/1043
RM0367 General-purpose timers (TIM2/TIM3)
546
21.4.19 TIM2 option register (TIM2_OR)
Address offset: 0x50
Reset value: 0x0000
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP ETR_RMP
rw rw rw rw rw
Bits 15:5 Reserved, must be kept at reset value.
Bits 4:3 TI4_RMP: Internal trigger (TI4 connected to TIM2_CH4) remap
This bit is set and cleared by software.
01: TIM2 TI4 input connected to COMP2_OUT
10: TIM2 TI4 input connected to COMP1_OUT
others: TIM2 TI4 input connected to ORed GPIOs. Refer to the Alternate function mapping
table in the device datasheets.
Bits 2:0 ETR_RMP: Timer2 ETR remap
This bit is set and cleared by software.
111: TIM2 ETR input is connected to COMP1_OUT
110: TIM2 ETR input is connected to COMP2_OUT
101: TIM2 ETR input is connected to LSE
100: TIM2 ETR input is connected to HSI48 (see note below)
011: TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set in Clock control
register (RCC_CR) (except for category 3 devices)
others: TIM2 ETR input is connected to ORed GPIOs. Refer to the Alternate function
mapping table in the device datasheets
Note: When TIM2 ETR is fed with HSI48, this ETR must be prescaled internally to the TIMER2
because the maximum system frequency is 32 MHz.