ST STM32L0x3 User Manual

RM0367 Rev 7 105/1043
RM0367 Flash program memory and data EEPROM (FLASH)
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Write while another write operation is ongoing
If the master requests a write operation while another one is ongoing, there are different
cases:
• If the previous write uses a Single programming operation or a Multiple programming
operation (half page) and all addresses/data have been sent to the memory interface,
and if the new write is in a protected area, the WRPERR flag is raised, the previous
write continues and the new write is deleted.
• If the previous write uses a Single programming operation or a Multiple programming
operation (half page) and all addresses/data have been sent to the memory interface,
and if the new Single programming operation or Multiple programming operation (half
page) is not in a protected area, the new write is put on hold and will be executed when
the first write operation is complete. It is important to emphasize that the master who
requested the second write is blocked until the first write completes and the second has
stored the address and data internally.
• It is forbidden to request a new write when a mass erase is ongoing: during all the
steps of the mass erase, the data is not stored internally and the new data can change
the value stored as a protection, adding unwanted protections.
• It is possible to change configurations to prepare a new write operation when the first
operation uses a Single programming operation or a Multiple programming operation
(half page) and all addresses/data have been sent to the memory interface.
3.6.3 Change the number of wait states while reading
To change the number of wait states, it is necessary to write to the FLASH_ACR register.
The read/write of a register uses a different interface than the memory read/write. The
number of wait states cannot be changed while the memory interface is reading and the
memory interface cannot be stopped if a request is sent to the register interface. For this
reason, while a master is reading the memory and another master changes the wait state
number, the register interface will be locked until the change takes effect (until the readings
stop). To stop the master which is changing the number of wait states, it is important to read
back the content of the FLASH_ACR register: it is not possible to know the number of clock
cycles that will be necessary to change the number of wait states as it depends on the
customer code.
3.6.4 Power-down
To put the NVM in power-down, it is necessary to execute an unlocking sequence.
The following sequence is used to unlock RUN_PD bit of the FLASH_ACR register:
• Write PDKEY1 = 0x04152637 to the FLASH_PDKEYR register.
• Write PEKEY2 = 0xFAFBFCFD to the FLASH_PDKEYR register.
It is necessary to write the two keys without constraints about other read or write. No error is
generated if the wrong key is used: when both have been written, RUN_PD bit is unlocked
and can be written to 1, putting the NVM in power-down mode.
Resetting the RUN_PD flag to 0 (making the NVM available) automatically resets the
sequence and the two keys are requested to re-enable RUN_PD.

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English