Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367
906/1043 RM0367 Rev 7
The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,
22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to
reach the desired frequency, the linear divider needs to be programmed according to the
formulas below:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
f
S
= I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
f
S
= I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
When the master clock is disabled (MCKOE bit cleared):
f
S
= I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
f
S
= I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
Table 158 provides example precision values for different clock configurations.
Note: Other configurations are possible that allow optimum clock precision.
Table 158. Audio-frequency precision using standard 8 MHz HSE
I2SxCLK
(MHz)
Data
length
I2SDIV I2SODD MCLK Target fs(Hz) Real f
s
(kHz) Error
32 16 5 0 No 96000 100 4.1667%
32 32 2 0 No 96000 100 4.1667%
32 16 10 1 No 48000 47.619 0.7937%
32 32 5 0 No 48000 50 4.1667%
32 16 11 1 No 44100 43.478 1.4098%
32 32 5 1 No 44100 45.454 3.0715%
32 16 15 1 No 32000 32.258 0.8065%
32 32 8 0 No 32000 31.25 2.3430%
32 16 22 1 No 22050 22.222 0.7811%
32 32 11 1 No 22050 21.739 1.4098%
32 16 31 1 No 16000 15.873 0.7937%
32 32 15 1 No 16000 16.129 0.8065%
32 16 45 1 No 11025 10.989 0.3264%
32 32 22 1 No 11025 11.111 0.7811%
32 16 62 1 No 8000 8 0.0000%
32 32 31 1 No 8000 7.936 0.7937%
32 16 2 0 Yes 32000 31.25 2.3430%
32 32 2 0 Yes 32000 31.25 2.3430%
32 16 3 0 Yes 22050 20.833 5.5170%
32 32 3 0 Yes 22050 20.833 5.5170%
32 16 4 0 Yes 16000 15.625 2.3428%
32 32 4 0 Yes 16000 15.625 2.3428%
32 16 5 1 Yes 11025 11.363 3.0715%