RM0367 Rev 7 959/1043
RM0367 Debug support (DBG)
970
33.5 SWD port
33.5.1 SWD protocol introduction
This synchronous serial protocol uses two pins:
• SWCLK: clock from host to target
• SWDIO: bidirectional
The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 kΩ
recommended by Arm
®
). These pull-up resistors can be configured internally. No external
pull-up resistors are required. .
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.
33.5.2 SWD protocol sequence
Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target
Table 173. REV-ID values
REV_ID Cat. 3 devices Cat. 5 devices
0x1000 Rev A
0x1008 Rev Z -
0x1018 Rev Y -
0x1038 Rev X -
0x2000 - Rev B
0x2008 - Rev Z
Table 174. Packet request (8-bits)
Bit Name Description
0 Start Must be “1”
1 APnDP
0: DP Access
1: AP Access
2RnW
0: Write Request
1: Read Request
4:3 A[3:2]
Address field of the DP or AP registers (refer to Table 178 on
page 962)
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