RM0367 Rev 7 163/1043
RM0367 Power control (PWR)
172
6.3.10 Standby mode
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex
®
-M0+ Deepsleep mode, with the voltage regulator disabled. The V
CORE
domain is
consequently powered off. The PLL, the MSI, the HSI16 oscillator and the HSE oscillator
are also switched off. SRAM and register contents are lost except for the RTC registers,
RTC backup registers and Standby circuitry (see Figure 10).
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except for:
• Reset pad
• Wakeup pins (WKUP1, WKUP2, WKUP3)
• RTC functions (tamper, time-stamp, RTC Alarm out, RTC clock calibration out) on the
following I/Os:
– Category 3: PC13, PA0
– Category 5: PC13, PA0, PE6
Entering Standby mode
Refer to Section 6.3.5: Entering low-power mode and to Table 38 for details on how to enter
Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. Refer to
Section 25.3: IWDG functional description on page 636.
• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register
(see Section 7.3.21).
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR
register.
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RCC_CSR register.
Exiting Standby mode
The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG
Reset, a rising edge on WKUP pins (WUKP1, WKUP2 or WKUP3), an RTC alarm, a tamper
event, or a time-stamp event is detected.
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the
PWR_CSR register (see Section 6.4.2) indicates that the microcontroller was in Standby
mode. All registers are reset to their default value after a system reset except for the register
bits in the RTC domain (see Section 27.7: RTC registers, SBF status flag in the PWR power
control/status register (PWR_CSR), Control/status register (RCC_CSR) and Clock control
register (RCC_CR)).
Refer to Section 6.3.6: Exiting low-power mode and to Table 38 for more details on how to
exit Standby mode.
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