ST STM32L0x3

RM0367 Rev 7 491/1043
RM0367 General-purpose timers (TIM2/TIM3)
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Figure 121. Counter timing diagram, internal clock divided by 2
Figure 122. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
MS31190V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0003
0002
0001
0000
0001
0002
0003
0034 0035
MS31191V1
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
CNT_EN
Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow
0036 0035