Flash program memory and data EEPROM (FLASH) RM0367
108/1043 RM0367 Rev 7
3.7.2 Program and erase control register (FLASH_PECR)
Address offset: 0x04
Reset value: 0x0000 0007
This register can only be written after a good write sequence done in FLASH_PEKEYR,
resetting the PELOCK bit.
Bit 2 Reserved, must be kept at reset value
Bit 1 PRFTEN
This bit enables the prefetch. It is automatically reset every time the DISAB_BUF bit (in this
register) is set to 1. To know how the prefetch works, see the Fetch and prefetch section.
0: The prefetch is disabled.
1: The prefetch is enabled. The memory interface stores the last address fetched and tries to
read the next one when no other read or write operation is ongoing.
Bit 0 LATENCY
The value of this bit specifies if a 0 or 1 wait-state is necessary to read the NVM. The user must
write the correct value relative to the core frequency and the operation mode (power). The
correct value to use can be found in Table 13. No check is done to verify if the configuration is
correct.
To increase the clock frequency, the user has to change this bit to ‘1’, then to increase the
frequency. To reduce the clock frequency, the user has to decrease the frequency, then to
change this bit to ‘0’.
0: Zero wait state is used to read a word in the NVM.
1: One wait state is used to read a word in the NVM.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res.
NZDISABLE
Res. Res. Res. Res.
OBL_LAUNCH
ERRIE
EOPIE
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PARRALELBANK
Res. Res. Res. Res.
FPRG
ERASE
FIX
Res. Res. Res.
DATA
PROG
OPT_LOCK
PRG_LOCK
PE_LOCK
rw rw rw rw rw rw rs rs rs
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