RM0367 Rev 7 95/1043
RM0367 Flash program memory and data EEPROM (FLASH)
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Status register
The FLASH_SR Status Register gives some information on the memory interface or the
NVM status (operation(s) ongoing) and about errors that happened.
BSY
This flags is set and reset by hardware. It is set to 1 every time the memory interface
executes a write/erase operation, and it informs that no other operation can be executed. If
a new operation is requested, different behaviors can occur:
• Waiting for read, or waiting for write/erase, or waiting for option loading:
If the software requests a write operation while a write/erase operation is executing
(HVOFF = 0), the memory interface stalls the master and has the pending operation
execute as soon as the write/erase operation is complete.
• Hard fault:
If the software requests a data read in a half-page operation when the memory
interface is waiting for the next address/data (BSY is already 1 but HVOFF = 0), the
memory interface generates a hard fault (because it cannot execute the read) and
continues to wait for missing addresses.
• RDERR error:
If the software requests a read operation while a write/erase operation is executing
(HVOFF = 0) but the address is protected, the memory interface rises the flag and
continues to wait for the end of the write/erase operation.
• Write abort:
If the software fetches in the NVM when the memory interface is waiting for an
address/data in a half-page operation, the write/erase operation is aborted, the
FWWERR flag is raised and the fetch is executed.
EOP
This flag is set by hardware and reset by software. The software can reset it writing 1 in the
status register. This bit is set when the write/erase operation is completed and the memory
interface can work on other operations (or start to work on pending operations).
It is useful to clear it before starting a new write/erase operation, in order to know when the
actual operation is complete. It is very important to wait for this flag to rise when a mass
erase is ongoing, before requesting a new operation.
HVOFF
This flag is set and reset by hardware and it is a memory interface information copy coming
from the NVM: it informs when the High-Voltage Regulators are on (= 0) or off (= 1).
PGAERR
This flag is set by hardware and reset by software. It informs when an alignment error
happened. It is raised when:
• The first address in a half-page operation is not aligned to a half-page (lower 6 bits
equal to zero).
• A half-page change happened in a half-page operation (the addresses from 2 to 16 in a
half-page operation are not in the same half-page, selected by the first address).
An alignment error aborts the write/erase operation and an interrupt can be generated (if
ERRIE = 1 in the FLASH_PECR register). The content of the NVM is not changed.
If this flag is set, the memory interface blocks all other half-page operations.
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