Analog-to-digital converter (ADC) RM0367
330/1043 RM0367 Rev 7
Figure 53. Analog watchdog threshold update
14.8 Oversampler
The oversampling unit performs data preprocessing to offload the CPU. It can handle
multiple conversions and average them into a single data with increased data width, up to
16-bit.
It provides a result with the following form, where N and M can be adjusted:
It allows the following functions to be performed by hardware: averaging, data rate
reduction, SNR improvement, basic filtering.
The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register. It
can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits.
It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register.
For code example, refer to A.8.15: Oversampling code example.
The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right.
The upper bits of the result are then truncated, keeping only the 16 least significant bits
rounded to the nearest value using the least significant bits left apart by the shifting, before
being finally transferred into the ADC_DR data register.
Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are
simply truncated.
MSv65329V1
ADC state Conversion Conversion
LT, HT XXXX
Comparison
Active
XXXY
Masked
Threshould updated
Conversion
Active
XXXZ
Conversion
Result
1
M
-----
Conversion t
n
()
n0=
nN1–=
×=
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