ST STM32L0x3 - Figure 167. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0 X36; Figure 168. Counter Timing Diagram, Internal Clock Divided by N

General-purpose timers (TIM21/22) RM0367
560/1043 RM0367 Rev 7
Figure 167. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 168. Counter timing diagram, internal clock divided by N
0034 0035
MS31191V1
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
CNT_EN
Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow
0036 0035
00
1F
20
MS31192V1
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
01