ST STM32L0x3 User Manual

RM0367 Rev 7 217/1043
RM0367 Reset and clock control (RCC)
225
7.3.20 Clock configuration register (RCC_CCIPR)
Address: 0x4C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 11 WWDGSMEN: Window watchdog clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Window watchdog clock disabled in Sleep mode
1: Window watchdog clock enabled in Sleep mode (if enabled by WWDGEN)
Bit 10 Reserved, must be kept at reset value.
Bit 9 LCDSMEN: LCD clock enable during Sleep mode bit
This bit is set and cleared by software.
0: LCD clock disabled in Sleep mode
1: LCD clock enabled in Sleep mode (if enabled by LCDEN)
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: Timer 7 clock enable during Sleep mode bit
Set and cleared by software.
0: Timer 7 clock disabled in Sleep mode
1: Timer 7 clock enabled in Sleep mode (if enabled by TIM7EN)
Bit 4 TIM6SMEN: Timer 6 clock enable during Sleep mode bit
Set and cleared by software.
0: Timer 6 clock disabled in Sleep mode
1: Timer 6 clock enabled in Sleep mode (if enabled by TIM6EN)
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3SMEN: Timer3 clock enable during Sleep mode bit
Set and cleared by software.
0: Timer3 clock disabled in Sleep mode
1: Timer3 clock enabled in Sleep mode (if enabled by TIM3EN)
Bit 0 TIM2SMEN: Timer2 clock enable during Sleep mode bit
Set and cleared by software.
0: Timer2 clock disabled in Sleep mode
1: Timer2 clock enabled in Sleep mode (if enabled by TIM2EN)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res.
HSI48SE
L
Res. Res. Res. Res. Res. Res.
LPTIM1
SEL1
LPTIM1S
EL0
I2C3SE
L1
I2C3SE
L0
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res.
I2C1
SEL1
I2C1
SEL0
LPUART1
SEL1
LPUART1
SEL0
Res. Res. Res. Res. Res. Res.
USART2
SEL1
USART2
SEL0
USART1
SEL1
USART1
SEL0
rw rw rw rw rw rw rw rw

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English