ST STM32L0x3 User Manual

Independent watchdog (IWDG) RM0367
640/1043 RM0367 Rev 7
25.4.2 IWDG prescaler register (IWDG_PR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR[2:0]
rw rw rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 PR[2:0]: Prescaler divider
These bits are write access protected see Section 25.3.4: Register access protection. They
are written by software to select the prescaler divider feeding the counter clock. PVU bit of
the IWDG status register (IWDG_SR) must be reset in order to be able to change the
prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the V
DD
voltage domain. This
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG
status register (IWDG_SR) is reset.

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English