Analog-to-digital converter (ADC) RM0367
338/1043 RM0367 Rev 7
14.12.2 ADC interrupt enable register (ADC_IER)
Address offset: 0x04
Reset value: 0x0000 0000
Bit 2 EOC: End of conversion flag
This bit is set by hardware at the end of each conversion of a channel when a new data result is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register.
0: Channel conversion not complete (or the flag event was already acknowledged and cleared by
software)
1: Channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by
software by programming it to ‘1’.
0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches
a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res.
EOCAL
IE
Res. AWDIE Res. Res. OVRIE EOSIE EOCIE
EOSMP
IE
ADRDY
IE
rw rw rw rw rw rw rw
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCALIE: End of calibration interrupt enable
This bit is set and cleared by software to enable/disable the end of calibration interrupt.
0: End of calibration interrupt disabled
1: End of calibration interrupt enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures
that no conversion is ongoing).
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 Reserved, must be kept at reset value.
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