Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367
878/1043 RM0367 Rev 7
Figure 282. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode)
1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 31.3.5: Slave select (NSS) pin management.
2. An accidental input information is captured at the input of transmitter Rx shift register. All the events
associated with the transmitter receive flow must be ignored in standard transmit only mode (e.g. OVF
flag).
3. In this configuration, both the MISO pins can be used as GPIOs.
Note: Any simplex communication can be alternatively replaced by a variant of the half-duplex
communication with a constant setting of the transaction direction (bidirectional mode is
enabled while BDIO bit is not changed).
Rx shift register
Tx shift register Rx shift register
Tx shift register
SPI clock
generator
Master
Slave
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
NSS
(1) (1)
(2)
MSv39625V1
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