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General-purpose timers (TIM21/22) RM0367

574/1043 RM0367 Rev 7

Hints on using center-aligned mode

• When starting in center-aligned mode, the current up-down configuration is used. It

means that the counter counts up or down depending on the value written in the DIR bit

in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the

same time by the software.

• Writing to the counter while running in center-aligned mode is not recommended as it

can lead to unexpected results. In particular:

– The direction is not updated if a value greater than the auto-reload value is written

in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting

up, it continues to count up.

– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no

Update Event UEV is generated.

• The safest way to use center-aligned mode is to generate an update by software

(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to

write the counter while it is running.

22.3.10 Clearing the OCxREF signal on an external event

The OCxREF signal for a given channel can be driven Low by applying a High level to the

ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The

OCxREF signal remains Low until the next update event, UEV, occurs.

This function can only be used in output compare and PWM modes, and does not work in

forced mode.

For example, the ETR signal can be connected to the output of a comparator to be used for

current handling. In this case, the ETR must be configured as follow:

1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR

2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to

‘0’.

3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be

configured according to the user needs.

For code example, refer to A.11.10: ETR configuration to clear OCxREF code example.

Figure 183 shows the behavior of the OCxREF signal when the ETRF Input becomes High,

for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in

PWM mode.

ST STM32L0x3 User Manual

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