General-purpose timers (TIM2/TIM3) RM0367
496/1043 RM0367 Rev 7
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 129 gives an overview of the external trigger input block.
Figure 129. External trigger input block
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
For code example, refer to A.11.2: Up counter on each 2 ETR rising edges code example.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
External clock
mode 1
Internal clock
mode
TRGI
CK_INT
CK_PSC
TIMx_SMCR
SMS[2:0]
MS33116V1
(internal clock)
TI1F or
TI2F or
or
Encoder
mode
External clock
mode 2
ETRF
ECE
0
1
TIMx_SMCR
ETP
ETR pin
ETR
Divider
/1, /2, /4, /8
Filter
downcounter
f
ETRP
TIMx_SMCR
ETPS[1:0]
TIMx_SMCR
ETF[3:0]
DTS
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