RM0367 Rev 7 81/1043
RM0367 Flash program memory and data EEPROM (FLASH)
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3.3.4 Writing/erasing the NVM
There are many ways to change the NVM content. The memory interface helps to reduce
the possibility of unwanted changes and to implement by hardware all sequences necessary
to erase or write in the different memory areas.
Write/erase protocol
To write/erase memory content when the protections have been removed, the user needs
to:
1. configure the operation to execute,
2. send to the memory interface the right number of data, writing one or several
addresses in the NVM,
3. wait for the operation to complete.
During the waiting time, the user can prepare the next operation (except in very particular
cases) writing the new configuration and starting to write data for the next write/erase
operation.
The waiting time depends on the type of operation. A write/erase can last from Tprog (3.2
ms) to 2 x Tglob (3.7 ms) + Tprog (3.2 ms). The memory interface can be configured to write
a half-page (16 words in the Flash program memory) with only one waiting time. This can
reduce the time to program a big amount of data.
Two different protocols can be used: single programming and multiple programming
operation.
Single programming operation
With this protocol, the software has to write a value in a not-protected address of the NVM.
When the memory interface receives this writing request, it stalls the master for some
pulses of clock (for more details, see Table 17) while it checks the protections and the
previous value and it latches the new value inside the NVM. The software can then start to
configure the next operation. The operation will complete when the EOP bit of FLASH_SR
register rises (if it was 0 at the operation start). The operation time is resumed in Table 19
for all operations.
Multiple programming operation (half page)
You can write a half-page (16 words) in Flash program memory, To execute this protocol,
follow the next conditions:
• PGAERR bit in the FLASH_SR register has to be zero (no previous alignment errors).
• The first address has to be half-page aligned (the 6 lower bits of the address have to be
at zero).
• All 16 words must be in the same half-page (address bits 7 to 31 must be the same for
all 16 words). This means that the first address sets the half-page and the next ones
must be inside this half-page. The written data will be stored sequentially in the next
addresses. It is not important that the addresses increase or change (for example, the
same address can be used 16 times), as the memory interface will automatically
increase the address internally.
• Only words (32 bits) can be written.
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