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RM0367 Rev 7 267/1043

RM0367 Direct memory access controller (DMA)

288

Figure 27. DMA request mapping

Peripheral request signals

Internal

DMA request

Fixed hardware priority

High priority

Low priority

DMA

SW trigger 1

(MEM2MEM bit)

SW trigger 2

(MEM2MEM bit)

SW trigger 3

(MEM2MEM bit)

SW trigger 5

(MEM2MEM bit)

SW trigger 6

(MEM2MEM bit)

SW trigger 7

(MEM2MEM bit)

ADC, TIM2_CH3,AES_IN

ADC,SPI1_RX,USART1_TX,

LPUART1_TX,I2C1_TX,I2C3_TX,

TIM2_UP,TIM6_UP/DAC chan. 1,

AES_OUT,TIM3_CH3,

USART4_RX, USART5_RX

SPI1_TX, USART1_RX,I2C3_RX

LPUART1_RX, I2C1_RX,

TIM2_CH2, TIM3_CH4,TIM3_UP,

USART4_TX,USART5_TX,

AES_OUT

SPI2_RX, USART1_TX,

USART2_TX, I2C2_TX, I2C3_TX,

TIM2_CH4,TIM7_UP/DAC chan. 2

SPI2_TX, USART1_RX,

USART2_RX, I2C2_RX,

TIM2_CH1, TIM3_CH1, AES_IN,

I2C3_RX

SPI2_RX, USART2_RX,

LPUART1_RX, I2C1_TX,

TIM3_TRIG, USART4_RX,

USART5_RX

SPI2_TX, USART2_TX,

USART4_TX, USART5_TX,

LPUART1_TX, I2C1_RX,

TIM2_CH2, TIM2_CH4

SW trigger 4

(MEM2MEM bit)

MS33701V3

DMA_CSELR

C7S

C6S

C5S

C4S

C3S

C2S

C1S

Table 51. DMA requests for each channel

CxS[3:0] Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7

0000 ADC ADC ADC - - - - -

0001 SPI1 - SPI1_RX SPI1_TX - - - -

0010 SPI2 - - - SPI2_RX SPI2_TX SPI2_RX SPI2_TX

0011 USART1 -

USART1_

0100 USART2 -- -

USART2_

0101 LPUART1 -

LPUART1_

LPUART1

_RX

LPUART1_

0110 I2C1 - I2C1_TX I2C1_RX - - I2C1_TX I2C1_RX

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English

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