RM0367 Rev 7 167/1043
RM0367 Power control (PWR)
172
6.4 Power control registers
The peripheral registers have to be accessed by half-words (16-bit) or words (32-bit).
6.4.1 PWR power control register (PWR_CR)
Address offset: 0x00
Reset value: 0x0000 1000 (reset by wakeup from Standby mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
151413121110987654321 0
Res. LPRUN
DS_EE
_KOFF
VOS[1:0] FWU ULP DBP PLS[2:0] PVDE CSBF CWUF PDDS LPSDSR
rw rw rw rw rw rw rw rw rw rw rw rc_w1 rc_w1 rw rw
Bits 31:15 Reserved, always read as 0.
Bit 14 LPRUN: Low-power run mode
When LPRUN bit is set together with the LPSDSR bit, the regulator is switched from Main
mode to low-power mode. Otherwise, it remains in Main mode. The regulator goes back to
operate in Main mode when LPRUN is reset.
If this bit is set (with LPSDSR bit set) and the CPU enters sleep or Deepsleep mode (LP
sleep or Stop mode), then, when the CPU wakes up from these modes, it enters Run
mode but with LPRUN bit set. To enter again Low-power run mode, it is necessary to
perform a reset and set LPRUN bit again.
It is forbidden to reset LPSDSR when the MCU is in Low-power run mode. LPSDSR is
used as a prepositioning for the entry into low-power mode, indicating to the system which
configuration of the regulator will be selected when entering low-power mode. The
LPSDSR bit must be set before the LPRUN bit is set. LPSDSR can be reset only when
LPRUN bit=0.
0: Voltage regulator in Main mode in Low-power run mode
1: Voltage regulator in low-power mode in Low-power run mode
Bit 13 DS_EE_KOFF: Deepsleep mode with non-volatile memory kept off
When entering low-power mode (Stop or Standby only), if DS_EE_KOFF and RUN_PD
bits are both set in FLASH_ACR register (refer to Section 3.7.1: Access control register
(FLASH_ACR), the non-volatile memory (Flash program memory and data EEPROM) will
not be woken up when exiting from Deepsleep mode.
0: NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set
1: NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set)
Bits 12:11 VOS[1:0]: Voltage scaling range selection
These bits are used to select the internal regulator voltage range.
Before resetting the power interface by resetting the PWRRST bit in the RCC_APB1RSTR
register, these bits have to be set to ‘10’ and the frequency of the system has to be
configured accordingly.
00: forbidden (bits are unchanged and keep the previous value, no voltage change
occurs)
01: 1.8 V (range 1)
10: 1.5 V (range 2)
11: 1.2 V (range 3)