RM0367 Rev 7 173/1043
RM0367 Reset and clock control (RCC)
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7 Reset and clock control (RCC)
7.1 Reset
There are three types of reset, defined as system reset, power reset and RTC domain reset.
7.1.1 System reset
A system reset sets all registers to their reset values unless specified otherwise in the
register description.
A system reset is generated when one of the following events occurs:
• A low level on the NRST pin (external reset)
• Window watchdog end-of-count condition (WWDG reset)
• Independent watchdog end-of-count condition (IWDG reset)
• A software reset (SW reset) (see Software reset)
• Low-power management reset (see Low-power management reset)
• Option byte loader reset (see Option byte loader reset)
• Exit from Standby mode
• Firewall protection (see Section 5: Firewall (FW))
The reset source can be identified by checking the reset flags in the control/status register,
RCC_CSR (see Section 7.3.21).
Software reset
The SYSRESETREQ bit in Cortex
®
-M0+ AIRCR register (Application Interrupt and Reset
Control Register) must be set to force a software reset on the device. Refer to Arm
®
Cortex
®
-M0+ Technical Reference Manual for more details.
Low-power management reset
There are two ways to generate a low-power management reset:
• Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
• Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
Option byte loader reset
The Option byte loader reset is generated when the OBL_LAUNCH bit (bit 18) is set in the
FLASH_PECR register. This bit is used to launch by software the option byte loading.
For further information on the user option bytes, refer to Section 3: Flash program memory
and data EEPROM (FLASH).