ST STM32L0x3 - Figure 117. Counter Timing Diagram, Internal Clock Divided by 4; Figure 118. Counter Timing Diagram, Internal Clock Divided by N

To Next Page

To Previous Page

General-purpose timers (TIM2/TIM3) RM0367

488/1043 RM0367 Rev 7

Figure 117. Counter timing diagram, internal clock divided by 4

Figure 118. Counter timing diagram, internal clock divided by N

0000

0001

0000

MS31186V1

CK_PSC

Timerclock = CK_CNT

Counter register

Update event (UEV)

Counter underflow

Update interrupt flag

(UIF)

CNT_EN

001F20

MS31187V1