Direct memory access controller (DMA) RM0367
276/1043 RM0367 Rev 7
Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into
account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB
transfer as described below:
• An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is
converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.
• An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to
an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.
11.4.6 DMA error management
A DMA transfer error is generated when reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or write access, the faulty
channel x is automatically disabled through a hardware clear of its EN bit in the
corresponding DMA_CCRx register.
The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of
the DMA_CCRx register is set.
The EN bit of the DMA_CCRx register can not be set again by software (channel x re-
activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of
the DMA_IFCR register).
When the software is notified with a transfer error over a channel which involves a
peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any
pending or future DMA request. Then software may normally reconfigure both DMA and the
peripheral in DMA mode for a new transfer.
11.5 DMA interrupts
An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.
11.6 DMA registers
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The DMA registers have to be accessed by words (32-bit).
Table 53. DMA interrupt requests
Interrupt request Interrupt event Event flag
Interrupt
enable bit
Channel x interrupt
Half transfer on channel x HTIFx HTIEx
Transfer complete on channel x TCIFx TCIEx
Transfer error on channel x TEIFx TEIEx
Half transfer or transfer complete or transfer error on channel x GIFx -
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