ST STM32L0x3 User Manual

AES hardware accelerator (AES) RM0367
434/1043 RM0367 Rev 7
19.3 AES implementation
The device has a single instance of AES peripheral.
19.4 AES functional description
19.4.1 AES block diagram
Figure 84 shows the block diagram of AES.
Figure 84. AES block diagram
19.4.2 AES internal signals
Table 87 describes the user relevant internal signals interfacing the AES peripheral.
MSv42155V1
aes_hclk
Banked registers
DOUT
KEY
IVI
DIN
AES
key
control
status
IV, counter
data in
data out
aes_it
32-bit
AHB bus
aes_in_dma
AES_CR
AES_KEYRx
AES_SR
AES_IVRx
AES_DINR
AES_DOUTR
AES
Core
(AEA)
swap
AHB
interface
IRQ
interface
Control Logic
DMA
interface
aes_out_dma
32-bit
access
Table 87. AES internal input/output signals
Signal name Signal type Description
aes_hclk digital input AHB bus clock
aes_it digital output AES interrupt request
aes_in_dma
digital
input/output
Input DMA single request/acknowledge
aes_out_dma
digital
input/output
Output DMA single request/acknowledge

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English