ST STM32L0x3 User Manual

RM0367 Rev 7 205/1043
RM0367 Reset and clock control (RCC)
225
7.3.13 AHB peripheral clock enable register (RCC_AHBENR)
Address offset: 0x30
Reset value: 0x0000 0100
Access: no wait state, word, half-word and byte access
When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res.
CRYP
EN
Res. Res. Res.
RNGE
N
Res. Res. Res. TSCEN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res.
CRC
EN
Res. Res. Res.
MIF
EN
Res. Res. Res. Res. Res. Res. Res.
DMA
EN
rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 CRYPEN: Crypto clock enable bit
This bit is set and reset by software.
0: Crypto clock disabled
1: Crypto clock enabled
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 RNGEN: Random Number Generator clock enable bit
This bit is set and reset by software.
0: RNG clock disabled
1: RNG clock enabled
Bits 19:17 Reserved, must be kept at reset value.
Bit 16
TSCEN: Touch Sensing clock enable bit
This bit is set and reset by software.
0: Touch sensing clock disabled
1: Touch sensing clock enabled
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable bit
This bit is set and reset by software.
0: Test integration module clock disabled
1: Test integration module clock enabled
Bits 11:9 Reserved, must be kept at reset value.

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English