Direct memory access controller (DMA) RM0367
266/1043 RM0367 Rev 7
11.3 DMA implementation
11.3.1 DMA
DMA is implemented with the hardware configuration parameters shown in the table below.
11.3.2 DMA request mapping
DMA controller
The hardware requests from the peripherals (TIM2/6, ADC, DAC, SPI1/2, I2C1/2, AES
(available only on category 3 and 5 devices, with AES), USART1/2 and LPUART1) are
mapped to the DMA channels through the DMA_CSELR channel selection registers (see
Figure 27).
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Caution: A same peripheral request can be assigned to two different channels only if the application
ensures that these channels are not requested to be served at the same time. In other
words, if two different channels receive a same asserted peripheral request at the same
time, an unpredictable DMA hardware behavior occurs.
Table 51 lists the DMA requests for each channel.
Table 50. DMA implementation
Feature DMA
Number of channels 7
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