General-purpose I/Os (GPIO) RM0367
242/1043 RM0367 Rev 7
The LOCK sequence (refer to Section 9.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A to E and H)) can only be performed using a word (32-bit long)
access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set
at the same time as the [15:0] bits.
For code example, refer to A.5.1: Locking mechanism code example.
For more details refer to LCKR register description in Section 9.4.8: GPIO port configuration
lock register (GPIOx_LCKR) (x = A to E and H).
9.3.7 I/O alternate function input/output
Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin refer to the device datasheet.
For code example, refer to A.5.2: Alternate function selection sequence code example.
9.3.8 External interrupt/wakeup lines
All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode.
Refer to Section 13: Extended interrupt and event controller (EXTI) and to Section 13.3.2:
Wakeup event management.
9.3.9 Input configuration
When the I/O port is programmed as input:
• The output buffer is disabled
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register provides the I/O state
Figure 23 shows the input configuration of the I/O port bit.
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