Analog-to-digital converter (ADC) RM0367
342/1043 RM0367 Rev 7
14.12.4 ADC configuration register 1 (ADC_CFGR1)
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. AWDCH[4:0] Res. Res. AWDEN AWDSGL Res. Res. Res. Res. Res. DISCEN
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTOFF WAIT CONT OVRMOD EXTEN[1:0] Res. EXTSEL[2:0] ALIGN RES[1:0]
SCAND
IR
DMAC
FG
DMAEN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 AWDCH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10001: ADC analog input Channel 17 monitored by AWD
10010: ADC analog input Channel 18 monitored by AWD
Others: Reserved
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR
register.
The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 AWDEN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog disabled
1: Analog watchdog enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 22 AWDSGL: Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel
identified by the AWDCH[4:0] bits or on all the channels
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bits 21:17 Reserved, must be kept at reset value.
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