RM0367 Rev 7 191/1043
RM0367 Reset and clock control (RCC)
225
7.3.3 Clock recovery RC register (RCC_CRRCR)
Address: 0x08
Reset value: 0x0000 XX00
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48CAL[7:0] Res. Res. Res. Res. Res.
HSI48
DIV6EN
HSI48RDY HSI48ON
r rrrrr r r rw r rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 HSI48CAL[7:0]: 48 MHz HSI clock calibration
These bits are read-only. They are set by hardware by loading option bytes during system
reset.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 HSI48DIV6EN: 48 MHz HSI clock divided by 6 output enable
This bit is set and cleared by software. When it is set, HSI48/6 clock is delivered to TIM3.
0: Output delivering HSI48/6 not enabled
1:Output delivering HSI48/6 enabled
Bit 1 HSI48RDY: 48MHz HSI clock ready flag
This bit is set by hardware to indicate that the 48 MHz RC oscillator is stable. It requires 6
48 MHz RC oscillator clock cycles to fall down after HSION reset.
0: 48 MHz HSI clock not ready
1: 48 MHz HSI clock ready
Bit 0 HSI48ON: 48MHz HSI clock enable bit
This bit is set and cleared by software.
0: 48 MHz HSI clock OFF
1: 48 MHz HSI clock ON
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