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System configuration controller (SYSCFG) RM0367

258/1043 RM0367 Rev 7

10.2.2 SYSCFG peripheral mode configuration register (SYSCFG_CFGR2)

Address offset: 0x04

Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res.

I2C3_

FMP

I2C2_FMP I2C1_FMP

I2C_PB9

_FMP

I2C_PB8

_FMP

I2C_PB7

_FMP

I2C_PB6

_FMP

Res. Res. LCD_CAPA[4:0] FWDIS

rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value

Bit 14 I2C3 FMP: I2C3 Fm+ drive capability enable bit

This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C3 pins

PC0, PC1, PA8 and PB4 selected through the IOPORT control registers AF selection bits.

Bit 13 I2C2 FMP: I2C2 Fm+ drive capability enable bit

This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C2 pins

PB13 and PB14 selected through the IOPORT control registers AF selection bits.

Bit 12 I2C1 FMP: I2C1 Fm+ drive capability enable bit

This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C1 pins

selected through the IOPORT control registers AF selection bits. This bit is bit is OR-ed with

I2C_PBx_FMP bits.

Bit 11 I2C PB9 FMP: Fm+ drive capability on PB9 enable bit

This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB9.

Bit 10 I2C PB8 FMP: Fm+ drive capability on PB8 enable bit

This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB8.

Bit 9 I2C PB7 FMP: Fm+ drive capability on PB7 enable bit

This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB7.

Bit 8 I2C PB6 FMP: Fm+ drive capability on PB6 enable bit

This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB6.

ST STM32L0x3 User Manual

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