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Inter-integrated circuit (I2C) interface RM0367

718/1043 RM0367 Rev 7

Figure 225. Master clock generation

Caution: In order to be I

C or SMBus compliant, the master clock must respect the timings given the

table below.

MS19858V1

SYNC1

SCL high level detected

SCLH counter starts

SCLH

SCL

SCL master clock generation

SCL released

SCL low level detected

SCLL counter starts

SCL driven low

SCLL

SYNC2

SCL master clock synchronization

SCLL

SCL driven low by

another device

SCL low level detected

SCLL counter starts

SCL released

SCLH

SCL high level detected

SCLH counter starts

SCL high level detected

SCLH counter starts

SCL low level detected

SCLL counter starts

SCLL

SCL driven low by

another device

SCLH

SCL high level detected

SCLH counter starts

Main Page

Table of Contents2
Documentation Conventions52
General Information52
List of Abbreviations for Registers52
Glossary53
Availability of Peripherals53
Product Category Definition53
Table 1. Stm32L0X3 Memory Density54
Table 2. Overview of Features Per Category54
System and Memory Overview56
System Architecture56
Figure 1. System Architecture56
S0: Cortex®-Bus57
S1: DMA-Bus57
Busmatrix57
AHB/APB Bridges57
Memory Organization58
Introduction58
Memory Map and Register Boundary Addresses59
Figure 2. Memory Map59
Table 3. Stm32L0X3 Peripheral Register Boundary Addresses60
Embedded SRAM64
Boot Configuration64
Table 4. Boot Modes64
Bank Swapping (Category 5 Devices Only)65
Physical Remap65
Embedded Bootloader65
Flash Program Memory and Data EEPROM (FLASH)66
Introduction66
NVM Main Features66
NVM Functional Description67
NVM Organization67
Table 5. NVM Organization (Category 3 Devices)67
Table 6. NVM Organization for UFB = 0 (192 Kbyte Category 5 Devices)68
Table 7. Flash Memory and Data EEPROM Remapping (192 Kbyte Category 5 Devices)69
Table 8. NVM Organization for UFB = 0 (128 Kbyte Category 5 Devices)69
Table 9. Flash Memory and Data EEPROM Remapping (128 Kbyte Category 5 Devices)70
Table 10. NVM Organization for UFB = 0 (64 Kbyte Category 5 Devices)70
Dual-Bank Boot Capability71
Table 11. Boot Pin and BFB2 Bit Configuration71
Reading the NVM72
Protocol to Read72
Relation between CPU Frequency/Operation Mode/Nvm Read Time73
Table 12. Link between Master Clock Power Range and Frequencies73
Table 13. Delays to Memory Access and Number of Wait States73
Data Buffering75
Figure 3. Structure of One Internal Buffer75
Table 14. Internal Buffer Management76
Figure 4. Timing to Fetch and Execute Instructions with Prefetch Disabled77
Table 15. Configurations for Buffers and Speculative Reading79
Figure 5. Timing to Fetch and Execute Instructions with Prefetch Enabled79
Table 16. Dhrystone Performances in All Memory Interface Configurations80
Writing/Erasing the NVM81
Write/Erase Protocol81
Unlocking/Locking Operations82
Detailed Description of NVM Write/Erase Operations85
Parallel Write Half-Page Flash Program Memory91
Table 17. NVM Write/Erase Timings94
Table 18. NVM Write/Erase Duration94
Status Register95
Memory Protection96
RDP (Read out Protection)97
Pcrop (Proprietary Code Read-Out Protection)98
Table 19. Protection Level and Content of RDP Option Bytes98
Figure 6. RDP Levels98
Table 20. Link between Protection Bits of Flash_Wrprotx Register and Protected Address in Flash Program Memory99
Protections against Unwanted Write/Erase Operations100
Table 21. Memory Access Vs Mode, Protection and Flash Program Memory Sectors100
Write/Erase Protection Management101
Protection Errors102
Write Protection Error Flag (WRPERR)102
Read Error (RDERR)102
NVM Interrupts102
Hard Fault103
Memory Interface Management103
Operation Priority and Evolution103
Read103
Write/Erase103
Table 22. Flash Interrupt Request103
Option Byte Loading104
Sequence of Operations104
Read as Data While Write104
Fetch While Write104
Write While Another Write Operation Is Ongoing105
Change the Number of Wait States While Reading105
Power-Down105
Flash Register Description106
Read Registers106
Write to Registers106
Access Control Register (FLASH_ACR)107
Program and Erase Control Register (FLASH_PECR)108
Power-Down Key Register (FLASH_PDKEYR)112
PECR Unlock Key Register (FLASH_PEKEYR)112
Program and Erase Key Register (FLASH_PRGKEYR)112
Option Bytes Unlock Key Register (FLASH_OPTKEYR)113
Status Register (FLASH_SR)114
Option Bytes Register (FLASH_OPTR)116
Write Protection Register 1 (FLASH_WRPROT1)118
Write Protection Register 2 (FLASH_WRPROT2)119
Flash Register Map120
Table 23. Flash Interface - Register Map and Reset Values120
Option Bytes121
Option Bytes Description121
Table 24. Option Byte Format121
Table 25. Option Byte Organization121
Mismatch When Loading Protection Flags122
Reloading Option Bytes by Software122
Cyclic Redundancy Check Calculation Unit (CRC)123
Introduction123
CRC Main Features123
CRC Functional Description124
CRC Block Diagram124
CRC Internal Signals124
CRC Operation124
Table 26. CRC Internal Input/Output Signals124
Figure 7. CRC Calculation Unit Block Diagram124
Polynomial Programmability125
CRC Registers126
CRC Data Register (CRC_DR)126
CRC Independent Data Register (CRC_IDR)126
CRC Control Register (CRC_CR)127
CRC Initial Value (CRC_INIT)128
CRC Polynomial (CRC_POL)128
CRC Register Map129
Table 27. CRC Register Map and Reset Values129
Firewall (FW)130
Introduction130
Firewall Main Features130
Firewall Functional Description131
Firewall AMBA Bus Snoop131
Functional Requirements131
Debug Consideration131
Figure 8. Stm32L0X3 Firewall Connection Schematics131
Write Protection132
Interrupts Management132
Firewall Segments132
Code Segment132
Non-Volatile Data Segment132
Volatile Data Segment133
Segment Accesses and Properties133
Segment Access Depending on the Firewall State133
Table 28. Segment Accesses According to the Firewall State133
Segments Properties134
Firewall Initialization134
Table 29. Segment Granularity and Area Ranges134
Firewall States135
Figure 9. Firewall Functional States135
Opening the Firewall136
Closing the Firewall136
Firewall Registers137
Code Segment Start Address (FW_CSSA)137
Code Segment Length (FW_CSL)137
Non-Volatile Data Segment Start Address (FW_NVDSSA)138
Non-Volatile Data Segment Length (FW_NVDSL)138
Volatile Data Segment Start Address (FW_VDSSA)139
Volatile Data Segment Length (FW_VDSL)139
Configuration Register (FW_CR)140
Firewall Register Map141
Table 30. Firewall Register Map and Reset Values141
Power Control (PWR)142
Power Supplies142
Independent A/D and DAC Converter Supply and Reference Voltage143
On Packages with V REF+ Pin143
On Packages Without V REF+ Pin143
Figure 10. Power Supply Overview143
Independent LCD Supply144
RTC and RTC Backup Registers144
RTC Registers Access144
Voltage Regulator145
Dynamic Voltage Scaling Management145
Range 1145
Range 2 and 3146
Table 31. Performance Versus VCORE Ranges146
Figure 11. Performance Versus VDD and VCORE Range146
Dynamic Voltage Scaling Configuration147
Voltage Regulator and Clock Management When VDD Drops147
Below 1.71 V147
Voltage Regulator and Clock Management When Modifying the VCORE Range147
Voltage Range and Limitations When VDD Ranges from 1.71 V to 2.0 V148
Power Supply Supervisor148
Figure 12. Power Supply Supervisors149
Power-On Reset (Por)/Power-Down Reset (PDR)150
Brown out Reset (BOR)150
Figure 13. Power-On Reset/Power-Down Reset Waveform150
Programmable Voltage Detector (PVD)151
Figure 14. BOR Thresholds151
Internal Voltage Reference (VREFINT)152
Figure 15. PVD Thresholds152
Low-Power Modes153
Table 32. Summary of Low-Power Modes153
Behavior of Clocks in Low-Power Modes154
Sleep and Low-Power Sleep Modes154
Stop and Standby Modes154
Slowing down System Clocks155
Peripheral Clock Gating155
Low-Power Run Mode (LP Run)155
Entering Low-Power Run Mode155
Exiting Low-Power Run Mode156
Entering Low-Power Mode156
Exiting Low-Power Mode156
Sleep Mode157
I/O States in Sleep Mode157
Entering Sleep Mode157
Exiting Sleep Mode157
Table 33. Sleep-Now157
Low-Power Sleep Mode (LP Sleep)158
I/O States in Low-Power Sleep Mode158
Entering Low-Power Sleep Mode158
Table 34. Sleep-On-Exit158
Exiting Low-Power Sleep Mode159
Table 35. Sleep-Now (Low-Power Sleep)159
Stop Mode160
I/O States in Low-Power Sleep Mode160
Entering Stop Mode160
Table 36. Sleep-On-Exit (Low-Power Sleep)160
Exiting Stop Mode161
Table 37. Stop Mode162
Standby Mode163
I/O States in Standby Mode163
Entering Standby Mode163
Exiting Standby Mode163
Debug Mode164
Waking up the Device from Stop and Standby Modes Using the RTC164
And Comparators164
Table 38. Standby Mode164
RTC Auto-Wakeup (AWU) from the Stop Mode165
RTC Auto-Wakeup (AWU) from the Standby Mode165
Comparator Auto-Wakeup (AWU) from the Stop Mode166
Power Control Registers167
PWR Power Control Register (PWR_CR)167
PWR Power Control/Status Register (PWR_CSR)170
PWR Register Map172
Table 39. PWR - Register Map and Reset Values172
Reset and Clock Control (RCC)173
Reset173
System Reset173
Software Reset173
Low-Power Management Reset173
Option Byte Loader Reset173
Power Reset174
RTC and Backup Registers Reset174
Figure 16. Simplified Diagram of the Reset Circuit174
Clocks175
Figure 17. Clock Tree177
HSE Clock178
Table 40. HSE/LSE Clock Sources178
External Source (HSE Bypass)179
External Crystal/Ceramic Resonator (HSE Crystal)179
HSI16 Clock179
Calibration179
MSI Clock180
Calibration180
HSI48 Clock180
Pll181
LSE Clock182
External Source (LSE Bypass)182
LSI Clock182
LSI Measurement182
System Clock (SYSCLK) Selection183
System Clock Source Frequency Versus Voltage Range183
HSE Clock Security System (CSS)183
Table 41. System Clock Source Frequency183
LSE Clock Security System184
RTC and LCD Clock184
Watchdog Clock185
Clock-Out Capability185
Internal/External Clock Measurement Using TIM21185
Figure 18. Using TIM21 Channel 1 Input Capture to Measure185
Frequencies185
Clock-Independent System Clock Sources for TIM2/TIM21/TIM22186
RCC Registers187
Clock Control Register (RCC_CR)187
Internal Clock Sources Calibration Register (RCC_ICSCR)190
Clock Recovery RC Register (RCC_CRRCR)191
Clock Configuration Register (RCC_CFGR)192
Clock Interrupt Enable Register (RCC_CIER)194
Clock Interrupt Flag Register (RCC_CIFR)196
Clock Interrupt Clear Register (RCC_CICR)197
GPIO Reset Register (RCC_IOPRSTR)198
AHB Peripheral Reset Register (RCC_AHBRSTR)199
APB2 Peripheral Reset Register (RCC_APB2RSTR)200
APB1 Peripheral Reset Register (RCC_APB1RSTR)201
GPIO Clock Enable Register (RCC_IOPENR)204
AHB Peripheral Clock Enable Register (RCC_AHBENR)205
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)207
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)209
GPIO Clock Enable in Sleep Mode Register (RCC_IOPSMENR)212
AHB Peripheral Clock Enable in Sleep Mode Register (RCC_AHBSMENR)213
APB2 Peripheral Clock Enable in Sleep Mode Register (RCC_APB2SMENR)214
APB1 Peripheral Clock Enable in Sleep Mode Register (RCC_APB1SMENR)215
Clock Configuration Register (RCC_CCIPR)217
Control/Status Register (RCC_CSR)219
RCC Register Map223
Table 42. RCC Register Map and Reset Values223
Clock Recovery System (CRS)226
Introduction226
CRS Main Features226
CRS Implementation226
Table 43. CRS Features226
CRS Functional Description227
CRS Block Diagram227
Synchronization Input227
Figure 19. CRS Block Diagram227
Frequency Error Measurement228
Figure 20. CRS Counter Behavior228
Frequency Error Evaluation and Automatic Trimming229
CRS Initialization and Configuration229
RELOAD Value229
FELIM Value230
CRS Low-Power Modes230
CRS Interrupts230
Table 44. Effect of Low-Power Modes on CRS230
Table 45. Interrupt Control Bits230
CRS Registers231
CRS Control Register (CRS_CR)231
CRS Configuration Register (CRS_CFGR)232
CRS Interrupt and Status Register (CRS_ISR)233
CRS Interrupt Flag Clear Register (CRS_ICR)235
CRS Register Map236
Table 46. CRS Register Map and Reset Values236
General-Purpose I/Os (GPIO)237
Introduction237
GPIO Main Features237
GPIO Functional Description237
Figure 21. Basic Structure of an I/O Port Bit238
Figure 22. Basic Structure of a 5-Volt Tolerant I/O Port Bit238
General-Purpose I/O (GPIO)239
Table 47. Port Bit Configuration Table239
I/O Pin Alternate Function Multiplexer and Mapping240
I/O Port Control Registers241
I/O Port Data Registers241
I/O Data Bitwise Handling241
GPIO Locking Mechanism241
I/O Alternate Function Input/Output242
External Interrupt/Wakeup Lines242
Input Configuration242
Output Configuration243
Figure 23. Input Floating/Pull Up/Pull down Configurations243
Alternate Function Configuration244
Figure 24. Output Configuration244
Analog Configuration245
Figure 25. Alternate Function Configuration245
Figure 26. High Impedance-Analog Configuration245
Using the HSE or LSE Oscillator Pins as Gpios246
Using the GPIO Pins in the RTC Supply Domain246
GPIO Registers246
GPIO Port Mode Register (Gpiox_Moder)246
(X =A to E and H)246
GPIO Port Output Type Register (Gpiox_Otyper)247
(X = a to E and H)247
GPIO Port Output Speed Register (Gpiox_Ospeedr)247
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)248
(X = a to E and H)248
GPIO Port Input Data Register (Gpiox_Idr)248
GPIO Port Output Data Register (Gpiox_Odr)249
(X = a to E and H)249
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr)249
GPIO Port Configuration Lock Register (Gpiox_Lckr)249
GPIO Alternate Function Low Register (Gpiox_Afrl)251
(X = a to E and H)251
GPIO Alternate Function High Register (Gpiox_Afrh)251
GPIO Port Bit Reset Register (Gpiox_Brr) (X = a to E and H)252
GPIO Register Map253
Table 48. GPIO Register Map and Reset Values253
System Configuration Controller (SYSCFG)255
Introduction255
SYSCFG Registers256
SYSCFG Memory Remap Register (SYSCFG_CFGR1)256
SYSCFG Peripheral Mode Configuration Register (SYSCFG_CFGR2)258
Reference Control and Status Register (SYSCFG_CFGR3)259
SYSCFG External Interrupt Configuration Register 1261
(Syscfg_Exticr1)261
SYSCFG External Interrupt Configuration Register 2262
(Syscfg_Exticr2)262
(Syscfg_Exticr3)262
SYSCFG External Interrupt Configuration Register 4263
(Syscfg_Exticr4)263
SYSCFG Register Map263
Table 49. SYSCFG Register Map and Reset Values263
Direct Memory Access Controller (DMA)265
Introduction265
DMA Main Features265
DMA Implementation266
Dma266
DMA Request Mapping266
DMA Controller266
Table 50. DMA Implementation266
Table 51. DMA Requests for each Channel267
Figure 27. DMA Request Mapping267
DMA Functional Description268
DMA Block Diagram268
DMA Transfers269
Figure 28. DMA Block Diagram269
DMA Arbitration270
DMA Channels271
Programmable Data Sizes271
Pointer Incrementation271
Channel Configuration Procedure272
Channel State and Disabling a Channel272
Circular Mode (in Memory-To-Peripheral/Peripheral-To-Memory Transfers)273
Memory-To-Memory Mode273
Peripheral-To-Peripheral Mode274
Programming Transfer Direction, Assigning Source/Destination274
DMA Data Width, Alignment and Endianness274
Addressing AHB Peripherals Not Supporting Byte/Half-Word Write Transfers275
Table 52. Programmable Data Width and Endian Behavior (When PINC = MINC = 1)275
DMA Error Management276
DMA Interrupts276
DMA Registers276
Table 53. DMA Interrupt Requests276
DMA Interrupt Status Register (DMA_ISR)277
DMA Interrupt Flag Clear Register (DMA279
DMA Channel X Configuration Register (Dma_Ccrx)280
DMA Channel X Number of Data to Transfer Register (Dma_Cndtrx)283
DMA Channel X Peripheral Address Register (Dma_Cparx)284
DMA Channel X Memory Address Register (Dma_Cmarx)284
DMA Channel Selection Register (DMA_CSELR)286
DMA Register Map286
Table 54. DMA Register Map and Reset Values286
Nested Vectored Interrupt Controller (NVIC)289
Main Features289
Systick Calibration Value Register289
Interrupt and Exception Vectors289
Extended Interrupt and Event Controller (EXTI)292
Introduction292
EXTI Main Features292
EXTI Functional Description292
EXTI Block Diagram293
Wakeup Event Management293
Figure 29. Extended Interrupts and Events Controller (EXTI) Block Diagram293
Peripherals Asynchronous Interrupts294
Hardware Interrupt Selection294
Hardware Event Selection294
Software Interrupt/Event Selection294
EXTI Interrupt/Event Line Mapping295
Figure 30. Extended Interrupt/Event GPIO Mapping295
Table 56. EXTI Lines Connections296
EXTI Registers297
EXTI Interrupt Mask Register (EXTI_IMR)297
EXTI Event Mask Register (EXTI_EMR)297
EXTI Rising Edge Trigger Selection Register (EXTI_RTSR)298
Falling Edge Trigger Selection Register (EXTI_FTSR)299
EXTI Software Interrupt Event Register (EXTI_SWIER)299
EXTI Pending Register (EXTI_PR)300
EXTI Register Map301
Table 57. Extended Interrupt/Event Controller Register Map and Reset Values301
Analog-To-Digital Converter (ADC)302
Introduction302
ADC Main Features303
ADC Functional Description304
ADC Pins and Internal Signals304
Table 58. ADC Input/Output Pins304
Figure 31. ADC Block Diagram304
ADC Voltage Regulator (ADVREGEN)305
Analog Reference for the ADC Internal Voltage Regulator305
Table 59. ADC Internal Input/Output Signals305
Table 60. External Triggers305
ADVREG Enable Sequence306
ADVREG Disable Sequence306
Calibration (ADCAL)306
Figure 32. ADC Calibration307
Calibration Factor Forcing Software Procedure308
ADC On-Off Control (ADEN, ADDIS, ADRDY)308
Figure 33. Calibration Factor Forcing308
ADC Clock (CKMODE, PRESC[3:0], LFMEN)309
Figure 34. Enabling/Disabling the ADC309
Figure 35. ADC Clock Scheme309
Low Frequency310
Table 61. Latency between Trigger and Start of Conversion310
ADC Connectivity311
Figure 36. ADC Connectivity311
Configuring the ADC312
Channel Selection (CHSEL, SCANDIR)312
Temperature Sensor, VREFINT and LCD_VLCD1 Internal Channels312
Programmable Sampling Time (SMP)313
Single Conversion Mode (CONT = 0)313
Continuous Conversion Mode (CONT = 1)314
Starting Conversions (ADSTART)314
Timings315
Figure 37. Analog to Digital Conversion Time315
Figure 38. ADC Conversion Timings315
Stopping an Ongoing Conversion (ADSTP)316
Conversion on External Trigger and Trigger Polarity (EXTSEL, EXTEN)316
Table 62. Configuring the Trigger Polarity316
Figure 39. Stopping an Ongoing Conversion316
Discontinuous Mode (DISCEN)317
Programmable Resolution (RES) - Fast Conversion Mode317
End of Conversion, End of Sampling Phase (EOC, EOSMP Flags)318
End of Conversion Sequence (EOS Flag)318
Table 63. Tsar Timings Depending on Resolution318
Example Timing Diagrams319
Hardware/Software Triggers)319
Figure 40. Single Conversions of a Sequence, Software Trigger319
Figure 41. Continuous Conversion of a Sequence, Software Trigger319
Figure 42. Single Conversions of a Sequence, Hardware Trigger320
Figure 43. Continuous Conversions of a Sequence, Hardware Trigger320
Data Management321
Data Register and Data Alignment (ADC_DR, ALIGN)321
ADC Overrun (OVR, OVRMOD)321
Figure 44. Data Alignment and Resolution (Oversampling Disabled: OVSE = 0)321
Managing a Sequence of Data Converted Without Using the DMA322
Managing Converted Data Without Using the DMA Without Overrun322
Managing Converted Data Using the DMA322
Figure 45. Example of Overrun (OVR)322
DMA One Shot Mode (DMACFG = 0)323
DMA Circular Mode (DMACFG = 1)323
Low-Power Features324
Wait Mode Conversion324
Figure 46. Wait Mode Conversion (Continuous Mode, Software Trigger)324
Auto-Off Mode (AUTOFF)325
Figure 47. Behavior with WAIT = 0, AUTOFF = 1325
Analog Window Watchdog326
Adc_Tr)326
Description of the Analog Watchdog326
ADC_AWD1_OUT Output Signal Generation327
Table 64. Analog Watchdog Comparison327
Table 65. Analog Watchdog Channel Selection327
Figure 49. Analog Watchdog Guarded Area327
Figure 50. ADC_AWD1_OUT Signal Generation328
Analog Watchdog Threshold Control329
Figure 51. ADC_AWD1_OUT Signal Generation (AWD Flag Not Cleared by Software)329
Figure 52. ADC1_AWD_OUT Signal Generation (on a Single Channel)329
Oversampler330
Figure 53. Analog Watchdog Threshold Update330
Table 66. Maximum Output Results Vs N and M. Grayed Values Indicates Truncation331
Figure 54. 20-Bit to 16-Bit Result Truncation331
Figure 55. Numerical Example with 5-Bits Shift and Rounding331
ADC Operating Modes Supported When Oversampling332
Analog Watchdog332
Triggered Mode332
Temperature Sensor and Internal Reference Voltage333
Figure 56. Triggered Oversampling Mode (TOVS Bit = 1)333
Main Features334
Reading the Temperature334
Figure 57. Temperature Sensor and VREFINT Channel Block Diagram334
Calculating the Actual V335
Dda335
Converting a Supply-Relative ADC Measurement to an Absolute Voltage Value335
VLCD Voltage Monitoring336
ADC Interrupts336
Table 67. ADC Interrupts336
ADC Registers337
ADC Interrupt and Status Register (ADC_ISR)337
ADC Interrupt Enable Register (ADC_IER)338
ADC Control Register (ADC_CR)340
ADC Configuration Register 1 (ADC_CFGR1)342
ADC Configuration Register 2 (ADC_CFGR2)346
ADC Sampling Time Register (ADC_SMPR)347
ADC Watchdog Threshold Register (ADC_TR)348
ADC Channel Selection Register (ADC_CHSELR)348
ADC Data Register (ADC_DR)349
ADC Calibration Factor (ADC_CALFACT)349
ADC Common Configuration Register (ADC_CCR)350
ADC Register Map351
Table 68. ADC Register Map and Reset Values351
Digital-To-Analog Converter (DAC)353
Introduction353
DAC1 Main Features353
Table 69. DAC Pins354
Figure 58. DAC Block Diagram354
DAC Output Buffer Enable355
DAC Channel Enable355
Single Mode Functional Description355
DAC Data Format355
DAC Channel Conversion355
Figure 59. Data Registers in Single DAC Channel Mode355
Independent Trigger with Single LFSR Generation356
Independent Trigger with Single Triangle Generation356
Figure 60. Timing Diagram for Conversion with Trigger Disabled TEN = 0356
DAC Output Voltage357
DAC Trigger Selection357
Table 70. External Triggers357
Dual-Mode Functional Description358
DAC Data Format358
DAC Channel Conversion in Dual Mode358
Description of Dual Conversion Modes358
Figure 61. Data Registers in Dual DAC Channel Mode358
Independent Trigger Without Wave Generation359
Independent Trigger with Single LFSR Generation359
Independent Trigger with Different LFSR Generation359
Independent Trigger with Single Triangle Generation360
Independent Trigger with Different Triangle Generation360
Simultaneous Software Start360
Simultaneous Trigger Without Wave Generation360
Simultaneous Trigger with Single LFSR Generation361
Simultaneous Trigger with Different LFSR Generation361
Simultaneous Trigger with Single Triangle Generation361
Simultaneous Trigger with Different Triangle Generation362
DAC Output Voltage362
DAC Trigger Selection362
Noise Generation362
Figure 62. DAC LFSR Register Calculation Algorithm362
Triangle-Wave Generation363
Figure 63. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation363
Figure 64. DAC Triangle Wave Generation363
DMA Request364
DMA Underrun364
Figure 65. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation364
DAC Registers365
DAC Control Register (DAC_CR)365
DAC Software Trigger Register (DAC_SWTRIGR)369
DAC Channel1 12-Bit Right-Aligned Data Holding Register369
(Dac_Dhr12R1)369
DAC Channel1 12-Bit Left-Aligned Data Holding Register370
(Dac_Dhr12L1)370
DAC Channel1 8-Bit Right-Aligned Data Holding Register370
(Dac_Dhr8R1)370
DAC Channel2 12-Bit Right-Aligned Data Holding Register370
(Dac_Dhr12R2)370
DAC Channel2 12-Bit Left-Aligned Data Holding Register371
(Dac_Dhr12L2)371
DAC Channel2 8-Bit Right-Aligned Data Holding Register371
(Dac_Dhr8R2)371
Dual DAC 12-Bit Right-Aligned Data Holding Register372
(Dac_Dhr12Rd)372
15.10.10 Dual DAC 12-Bit Left-Aligned Data Holding Register372
(Dac_Dhr12Ld)372
15.10.11 Dual DAC 8-Bit Right-Aligned Data Holding Register372
(Dac_Dhr8Rd)372
DAC Channel1 Data Output Register (DAC_DOR1)373
DAC Channel2 Data Output Register (DAC_DOR2)373
DAC Status Register (DAC_SR)373
15.10.15 DAC Register Map375
Table 71. DAC Register Map and Reset Values375
Comparator (COMP)377
Introduction377
COMP Main Features377
COMP Functional Description378
COMP Block Diagram378
COMP Pins and Internal Signals378
Figure 66. Comparator 1 and 2 Block Diagrams378
COMP Reset and Clocks379
Comparator LOCK Mechanism379
Power Mode379
COMP Interrupts379
COMP Registers379
Comparator 1 Control and Status Register (COMP1_CSR)379
Comparator 2 Control and Status Register (COMP2_CSR)381
COMP Register Map383
Table 72. COMP Register Map and Reset Values383
Liquid Crystal Display Controller (LCD)384
Introduction384
Glossary384
LCD Main Features385
LCD Implementation386
LCD Functional Description386
General Description386
Table 73. Implementation386
Figure 67. LCD Controller Block Diagram386
Frequency Generator387
Table 74. Example of Frame Rate Calculation387
Common Driver388
COM Signal Bias388
COM Signal Duty389
Figure 68. 1/3 Bias, 1/4 Duty389
Figure 69. Static Duty Case 1390
Figure 70. Static Duty Case 2390
To 1 Mux391
Segment Driver391
In the Case of 1/4 or 1/8 Duty391
Figure 71. 1/2 Duty, 1/2 Bias391
Figure 72. 1/3 Duty, 1/3 Bias392
Figure 73. 1/4 Duty, 1/3 Bias393
Figure 74. 1/8 Duty, 1/4 Bias394
Blink395
Voltage Generator and Contrast Control395
LCD Supply Source395
Table 75. Blink Frequency395
LCD Intermediate Voltages396
LCD Drive Selection396
Figure 75. LCD Voltage Control397
External Decoupling398
Deadtime398
Table 76. Vlcdrail Connections to GPIO Pins398
Figure 76. Deadtime398
Double Buffer Memory399
COM and SEG Multiplexing399
Output Pins Versus Duty Modes399
Remapping Capability for Small Packages399
Summary of COM and SEG Functions Versus Duty and Remap400
Table 77. Remapping Capability400
Figure 77. SEG/COM Mux Feature Example403
Flowchart404
Figure 78. Flowchart Example404
LCD Low-Power Modes405
LCD Interrupts405
Start of Frame (SOF)405
Update Display Done (UDD)405
Table 78. LCD Behavior in Low-Power Modes405
Table 79. LCD Interrupt Requests405
LCD Registers406
LCD Control Register (LCD_CR)406
LCD Frame Control Register (LCD_FCR)407
LCD Status Register (LCD_SR)409
LCD Clear Register (LCD_CLR)410
LCD Display Memory (LCD_RAM)411
LCD Register Map412
Table 80. LCD Register Map and Reset Values412
Touch Sensing Controller (TSC)414
Introduction414
TSC Main Features414
TSC Functional Description415
TSC Block Diagram415
Surface Charge Transfer Acquisition Overview415
Figure 79. TSC Block Diagram415
Figure 80. Surface Charge Transfer Analog I/O Group Structure416
Reset and Clocks417
Table 81. Acquisition Sequence Summary417
Figure 81. Sampling Capacitor Voltage Variation417
Charge Transfer Acquisition Sequence418
Figure 82. Charge Transfer Acquisition Sequence418
Spread Spectrum Feature419
Max Count Error419
Table 82. Spread Spectrum Deviation Versus AHB Clock Frequency419
Figure 83. Spread Spectrum Variation Principle419
Sampling Capacitor I/O and Channel I/O Mode Selection420
Table 83. I/O State Depending on Its Mode and IODEF Bit Value420
Acquisition Mode421
I/O Hysteresis and Analog Switch Control421
TSC Low-Power Modes422
TSC Interrupts422
Table 84. Effect of Low-Power Modes on TSC422
Table 85. Interrupt Control Bits422
TSC Registers423
TSC Control Register (TSC_CR)423
TSC Interrupt Enable Register (TSC_IER)425
TSC Interrupt Clear Register (TSC_ICR)426
TSC Interrupt Status Register (TSC_ISR)427
TSC I/O Hysteresis Control Register (TSC_IOHCR)427
TSC I/O Analog Switch Control Register (TSC_IOASCR)428
TSC I/O Sampling Control Register (TSC_IOSCR)428
TSC I/O Channel Control Register (TSC_IOCCR)429
TSC I/O Group Control Status Register (TSC_IOGCSR)429
TSC I/O Group X Counter Register (Tsc_Iogxcr)430
TSC Register Map431
Table 86. TSC Register Map and Reset Values431
AES Hardware Accelerator (AES)433
Introduction433
AES Main Features433
AES Implementation434
AES Functional Description434
AES Block Diagram434
AES Internal Signals434
Table 87. AES Internal Input/Output Signals434
Figure 84. AES Block Diagram434
AES Cryptographic Core435
Overview435
Typical Data Processing435
Chaining Modes435
Electronic Codebook (ECB) Mode436
Figure 85. ECB Encryption and Decryption Principle436
Cipher Block Chaining (CBC) Mode437
Figure 86. CBC Encryption and Decryption Principle437
Counter (CTR) Mode438
AES Procedure to Perform a Cipher Operation438
Introduction438
Figure 87. CTR Encryption and Decryption Principle438
Initialization of AES439
Data Append439
Figure 88. STM32 Cryptolib AES Flowchart Example439
AES Decryption Key Preparation441
AES Ciphertext Stealing and Data Padding442
AES Task Suspend and Resume442
Figure 89. Encryption Key Derivation for ECB/CBC Decryption (Mode 2)442
AES Basic Chaining Modes (ECB, CBC)443
Overview443
Figure 90. Example of Suspend Mode Management443
Figure 91. ECB Encryption443
Figure 92. ECB Decryption444
Figure 93. CBC Encryption444
Figure 94. CBC Decryption445
ECB/CBC Encryption Sequence446
ECB/CBC Decryption Sequence446
Figure 95. ECB/CBC Encryption (Mode 1)446
Suspend/Resume Operations in ECB/CBC Modes447
Figure 96. ECB/CBC Decryption (Mode 3)447
Alternative Single ECB/CBC Decryption Using Mode 4448
AES Counter (CTR) Mode448
Overview448
CTR Encryption and Decryption449
Figure 97. Message Construction in CTR Mode449
Figure 98. CTR Encryption449
Table 88. CTR Mode Initialization Vector Definition450
Figure 99. CTR Decryption450
Suspend/Resume Operations in CTR Mode451
AES Data Registers and Data Swapping451
Data Input and Output451
Data Swapping451
Figure 100. 128-Bit Block Construction with Respect to Data Swap452
Data Padding453
AES Key Registers453
AES Initialization Vector Registers453
AES DMA Interface453
Table 89. Key Endianness in Aes_Keyrx Registers453
Data Input Using DMA454
Data Output Using DMA454
Table 90. DMA Channel Configuration for Memory-To-AES Data Transfer454
Figure 101. DMA Transfer of a 128-Bit Data Block During Input Phase454
DMA Operation in Different Operating Modes455
Table 91. DMA Channel Configuration for AES-To-Memory Data Transfer455
Figure 102. DMA Transfer of a 128-Bit Data Block During Output Phase455
AES Error Management456
Read Error Flag (RDERR)456
Write Error Flag (WDERR)456
AES Interrupts456
AES Processing Latency457
Table 92. AES Interrupt Requests457
Table 93. Processing Latency (in Clock Cycle)457
Figure 103. AES Interrupt Signal Generation457
AES Registers458
AES Control Register (AES_CR)458
AES Status Register (AES_SR)460
AES Data Input Register (AES_DINR)461
AES Data Output Register (AES_DOUTR)461
AES Key Register 0 (AES_KEYR0)462
AES Key Register 1 (AES_KEYR1)463
AES Key Register 2 (AES_KEYR2)463
AES Key Register 3 (AES_KEYR3)463
AES Initialization Vector Register 0 (AES_IVR0)464
AES Initialization Vector Register 1 (AES_IVR1)464
AES Initialization Vector Register 2 (AES_IVR2)465
AES Initialization Vector Register 3 (AES_IVR3)465
AES Register Map465
Table 94. AES Register Map and Reset Values465
True Random Number Generator (RNG)467
Introduction467
RNG Main Features467
RNG Functional Description468
RNG Block Diagram468
RNG Internal Signals468
Table 95. RNG Internal Input/Output Signals468
Figure 104. RNG Block Diagram468
Random Number Generation469
Figure 105. Entropy Source Model469
Noise Source470
Post Processing470
Output Buffer470
Health Checks471
RNG Initialization471
RNG Operation471
Normal Operations471
Low-Power Operations472
Software Post-Processing472
RNG Clocking472
Error Management472
Clock Error Detection472
Noise Source Error Detection473
RNG Low-Power Usage473
RNG Interrupts473
RNG Processing Time473
Table 96. RNG Interrupt Requests473
RNG Entropy Source Validation474
Introduction474
Validation Conditions474
Data Collection474
RNG Registers475
RNG Control Register (RNG_CR)475
RNG Status Register (RNG_SR)476
RNG Data Register (RNG_DR)477
RNG Register Map478
Table 97. RNG Register Map and Reset Map478
General-Purpose Timers (TIM2/TIM3)479
TIM2/TIM3 Introduction479
TIM2/TIM3 Main Features479
Figure 106. General-Purpose Timer Block Diagram480
TIM2/TIM3 Functional Description481
Time-Base Unit481
Prescaler Description481
Figure 107. Counter Timing Diagram with Prescaler Division Change from 1 to 2482
Figure 108. Counter Timing Diagram with Prescaler Division Change from 1 to 4482
Counter Modes483
Upcounting Mode483
Figure 109. Counter Timing Diagram, Internal Clock Divided by 1483
Figure 110. Counter Timing Diagram, Internal Clock Divided by 2484
Figure 111. Counter Timing Diagram, Internal Clock Divided by 4484
Figure 112. Counter Timing Diagram, Internal Clock Divided by N485
Figure 113. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)485
Downcounting Mode486
Figure 114. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)486
Figure 115. Counter Timing Diagram, Internal Clock Divided by 1487
Figure 116. Counter Timing Diagram, Internal Clock Divided by 2487
Figure 117. Counter Timing Diagram, Internal Clock Divided by 4488
Figure 118. Counter Timing Diagram, Internal Clock Divided by N488
Center-Aligned Mode (Up/Down Counting)489
Figure 119. Counter Timing Diagram, Update Event When Repetition Counter489
Is Not Used489
Figure 120. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6490
Figure 121. Counter Timing Diagram, Internal Clock Divided by 2491
Figure 122. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36491
Figure 123. Counter Timing Diagram, Internal Clock Divided by N492
Figure 124. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)492
Clock Selection493
Internal Clock Source (CK_INT)493
Figure 125. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)493
External Clock Source Mode 1494
Figure 126. Control Circuit in Normal Mode, Internal Clock Divided by 1494
Figure 127. TI2 External Clock Connection Example494
Figure 128. Control Circuit in External Clock Mode 1495
External Clock Source Mode 2496
Figure 129. External Trigger Input Block496
Capture/Compare Channels497
Figure 130. Control Circuit in External Clock Mode 2497
Figure 131. Capture/Compare Channel (Example: Channel 1 Input Stage)498
Figure 132. Capture/Compare Channel 1 Main Circuit498
Input Capture Mode499
Figure 133. Output Stage of Capture/Compare Channel (Channel 1)499
PWM Input Mode501
Figure 134. PWM Input Mode Timing501
Forced Output Mode502
Output Compare Mode502
PWM Mode503
Figure 135. Output Compare Mode, Toggle on OC1503
PWM Edge-Aligned Mode504
Figure 136. Edge-Aligned PWM Waveforms (ARR=8)504
Downcounting Configuration505
PWM Center-Aligned Mode505
Figure 137. Center-Aligned PWM Waveforms (ARR=8)506
One-Pulse Mode507
Figure 138. Example of One-Pulse Mode507
Particular Case: Ocx Fast Enable508
Clearing the Ocxref Signal on an External Event508
Encoder Interface Mode509
Figure 139. Clearing Timx Ocxref509
Table 98. Counting Direction Versus Encoder Signals510
Timer Input XOR Function511
Figure 140. Example of Counter Operation in Encoder Interface Mode511
Figure 141. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted511
Timers and External Trigger Synchronization512
Slave Mode: Reset Mode512
Figure 142. Control Circuit in Reset Mode512
Slave Mode: Gated Mode513
Figure 143. Control Circuit in Gated Mode513
Slave Mode: Trigger Mode514
Figure 144. Control Circuit in Trigger Mode514
Slave Mode: External Clock Mode 2 + Trigger Mode515
Timer Synchronization516
Using One Timer as Prescaler for Another Timer516
Figure 145. Control Circuit in External Clock Mode 2 + Trigger Mode516
Figure 146. Master/Slave Timer Example516
Using One Timer to Enable Another Timer517
Figure 147. Gating Timer y with OC1REF of Timer X518
Using One Timer to Start Another Timer519
Figure 148. Gating Timer y with Enable of Timer X519
Figure 149. Triggering Timer y with Update of Timer X520
Figure 150. Triggering Timer y with Enable of Timer X520
Starting 2 Timers Synchronously in Response to an External Trigger521
Figure 151. Triggering Timer X and y with Timer X TI1 Input521
Debug Mode522
TIM2/TIM3 Registers523
Timx Control Register 1 (Timx_Cr1)523
Timx Control Register 2 (Timx_Cr2)525
Timx Slave Mode Control Register (Timx_Smcr)526
Table 99. TIM2/TIM3 Internal Trigger Connection527
Timx Dma/Interrupt Enable Register (Timx_Dier)528
Timx Status Register (Timx_Sr)529
Timx Event Generation Register (Timx_Egr)531
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)532
Output Compare Mode532
Input Capture Mode533
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)535
Output Compare Mode535
Input Capture Mode536
Timx Capture/Compare Enable Register (Timx_Ccer)536
Table 100. Output Control Bit for Standard Ocx Channels537
Timx Counter (Timx_Cnt)538
Timx Prescaler (Timx_Psc)538
Timx Auto-Reload Register (Timx_Arr)538
Timx Capture/Compare Register 1 (Timx_Ccr1)539
Timx Capture/Compare Register 2 (Timx_Ccr2)539
Timx Capture/Compare Register 3 (Timx_Ccr3)540
Timx Capture/Compare Register 4 (Timx_Ccr4)540
Timx DMA Control Register (Timx_Dcr)541
Timx DMA Address for Full Transfer (Timx_Dmar)541
Example of How to Use the DMA Burst Feature542
TIM2 Option Register (TIM2_OR)543
TIM3 Option Register (TIM3_OR)544
Timx Register Map545
Table 101. TIM2/3 Register Map and Reset Values545
General-Purpose Timers (TIM21/22)547
Introduction547
TIM21/22 Main Features547
Figure 152. General-Purpose Timer Block Diagram (TIM21/22)548
TIM21/22 Functional Description549
Timebase Unit549
Prescaler Description549
Figure 153. Counter Timing Diagram with Prescaler Division Change from 1 to 2550
Counter Modes551
Upcounting Mode551
Figure 154. Counter Timing Diagram with Prescaler Division Change from 1 to 4551
Figure 155. Counter Timing Diagram, Internal Clock Divided by 1552
Figure 156. Counter Timing Diagram, Internal Clock Divided by 2553
Figure 157. Counter Timing Diagram, Internal Clock Divided by 4553
Figure 158. Counter Timing Diagram, Internal Clock Divided by N554
Preloaded)554
Downcounting Mode555
Preloaded)555
Figure 161. Counter Timing Diagram, Internal Clock Divided by 1556
Figure 162. Counter Timing Diagram, Internal Clock Divided by 2556
Figure 163. Counter Timing Diagram, Internal Clock Divided by 4557
Figure 164. Counter Timing Diagram, Internal Clock Divided by N557
Center-Aligned Mode (Up/Down Counting)558
Figure 165. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6559
Figure 166. Counter Timing Diagram, Internal Clock Divided by 2559
Figure 167. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36560
Figure 168. Counter Timing Diagram, Internal Clock Divided by N560
Figure 169. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)561
Figure 170. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)561
Clock Selection562
Internal Clock Source (CK_INT)562
Figure 171. Control Circuit in Normal Mode, Internal Clock Divided by 1562
Figure 172. TI2 External Clock Connection Example563
External Clock Source Mode 2564
Figure 173. Control Circuit in External Clock Mode 1564
Figure 174. External Trigger Input Block564
Capture/Compare Channels565
Figure 175. Control Circuit in External Clock Mode 2565
Figure 176. Capture/Compare Channel (Example: Channel 1 Input Stage)566
Figure 177. Capture/Compare Channel 1 Main Circuit566
Input Capture Mode567
Figure 178. Output Stage of Capture/Compare Channel (Channel 1 and 2)567
PWM Input Mode569
Figure 179. PWM Input Mode Timing569
Forced Output Mode570
Output Compare Mode570
PWM Mode571
Figure 180. Output Compare Mode, Toggle on OC1571
Figure 181. Edge-Aligned PWM Waveforms (ARR=8)572
PWM Center-Aligned Mode573
Figure 182. Center-Aligned PWM Waveforms (ARR=8)573
Hints on Using Center-Aligned Mode574
Clearing the Ocxref Signal on an External Event574
One-Pulse Mode575
Figure 183. Clearing Timx Ocxref575
Figure 184. Example of One Pulse Mode576
Particular Case: Ocx Fast Enable577
Encoder Interface Mode577
Table 102. Counting Direction Versus Encoder Signals578
Figure 185. Example of Counter Operation in Encoder Interface Mode578
TIM21/22 External Trigger Synchronization579
Slave Mode: Reset Mode579
Figure 186. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted579
Slave Mode: Gated Mode580
Figure 187. Control Circuit in Reset Mode580
Slave Mode: Trigger Mode581
Figure 188. Control Circuit in Gated Mode581
Timer Synchronization (TIM21/22)582
Debug Mode582
Figure 189. Control Circuit in Trigger Mode582
TIM21/22 Registers583
TIM21/22 Control Register 1 (Timx_Cr1)583
TIM21/22 Control Register 2 (Timx_Cr2)585
TIM21/22 Slave Mode Control Register (Timx_Smcr)586
Table 103. Timx Internal Trigger Connection588
TIM21/22 Interrupt Enable Register (Timx_Dier)589
TIM21/22 Status Register (Timx_Sr)589
TIM21/22 Event Generation Register (Timx_Egr)591
TIM21/22 Capture/Compare Mode Register 1 (Timx_Ccmr1)592
Output Compare Mode592
Input Capture Mode594
TIM21/22 Capture/Compare Enable Register (Timx_Ccer)595
TIM21/22 Counter (Timx_Cnt)596
TIM21/22 Prescaler (Timx_Psc)596
TIM21/22 Auto-Reload Register (Timx_Arr)596
Table 104. Output Control Bit for Standard Ocx Channels596
TIM21/22 Capture/Compare Register 1 (Timx_Ccr1)597
TIM21/22 Capture/Compare Register 2 (Timx_Ccr2)597
TIM21 Option Register (TIM21_OR)598
TIM22 Option Register (TIM22_OR)599
TIM21/22 Register Map600
Table 105. TIM21/22 Register Map and Reset Values600
Basic Timers (TIM6/7)602
Introduction602
TIM6/7 Main Features602
Figure 190. Basic Timer Block Diagram602
TIM6/7 Functional Description603
Time-Base Unit603
Prescaler Description603
Figure 191. Counter Timing Diagram with Prescaler Division Change from 1 to 2604
Figure 192. Counter Timing Diagram with Prescaler Division Change from 1 to 4604
Counting Mode605
Figure 193. Counter Timing Diagram, Internal Clock Divided by 1605
Figure 194. Counter Timing Diagram, Internal Clock Divided by 2606
Figure 195. Counter Timing Diagram, Internal Clock Divided by 4606
Figure 196. Counter Timing Diagram, Internal Clock Divided by N607
Preloaded)607
Clock Source608
Preloaded)608
Debug Mode609
Figure 199. Control Circuit in Normal Mode, Internal Clock Divided by 1609
TIM6/7 Registers610
TIM6/7 Control Register 1 (Timx_Cr1)610
TIM6/7 Control Register 2 (Timx_Cr2)611
TIM6/7 Dma/Interrupt Enable Register (Timx_Dier)611
TIM6/7 Status Register (Timx_Sr)612
TIM6/7 Event Generation Register (Timx_Egr)612
TIM6/7 Counter (Timx_Cnt)612
TIM6/7 Prescaler (Timx_Psc)613
TIM6/7 Auto-Reload Register (Timx_Arr)613
TIM6/7 Register Map614
Table 106. TIM6/7 Register Map and Reset Values614
Low-Power Timer (LPTIM)615
Introduction615
LPTIM Main Features615
LPTIM Implementation616
LPTIM Functional Description616
LPTIM Block Diagram616
Table 107. Stm32L0X3 LPTIM Features616
Figure 200. Low-Power Timer Block Diagram616
LPTIM Trigger Mapping617
LPTIM Reset and Clocks617
Glitch Filter617
Table 108. LPTIM1 External Trigger Connection617
Prescaler618
Table 109. Prescaler Division Ratios618
Figure 201. Glitch Filter Timing Diagram618
Trigger Multiplexer619
Operating Mode619
One-Shot Mode619
Continous Mode620
Figure 202. LPTIM Output Waveform, Single Counting Mode Configuration620
Figure 203. LPTIM Output Waveform, Single Counting Mode Configuration620
And Set-Once Mode Activated (WAVE Bit Is Set)620
Timeout Function621
Waveform Generation621
Figure 204. LPTIM Output Waveform, Continuous Counting Mode Configuration621
Register Update622
Figure 205. Waveform Generation622
Counter Mode623
Timer Enable624
Encoder Mode624
Table 110. Encoder Counting Scenarios624
Debug Mode625
LPTIM Low-Power Modes625
Table 111. Effect of Low-Power Modes on the LPTIM625
Figure 206. Encoder Mode Counting Sequence625
LPTIM Interrupts626
LPTIM Registers626
Table 112. Interrupt Events626
LPTIM Interrupt and Status Register (LPTIM_ISR)627
LPTIM Interrupt Clear Register (LPTIM_ICR)628
LPTIM Interrupt Enable Register (LPTIM_IER)628
LPTIM Configuration Register (LPTIM_CFGR)629
LPTIM Control Register (LPTIM_CR)632
LPTIM Compare Register (LPTIM_CMP)633
LPTIM Autoreload Register (LPTIM_ARR)634
LPTIM Counter Register (LPTIM_CNT)634
LPTIM Register Map635
Table 113. LPTIM Register Map and Reset Values635
Independent Watchdog (IWDG)636
Introduction636
IWDG Main Features636
IWDG Functional Description636
IWDG Block Diagram636
Figure 207. Independent Watchdog Block Diagram636
Window Option637
Configuring the IWDG When the Window Option Is Enabled637
Configuring the IWDG When the Window Option Is Disabled637
Hardware Watchdog638
Register Access Protection638
Debug Mode638
IWDG Registers639
IWDG Key Register (IWDG_KR)639
IWDG Prescaler Register (IWDG_PR)640
IWDG Reload Register (IWDG_RLR)641
IWDG Status Register (IWDG_SR)642
IWDG Window Register (IWDG_WINR)643
IWDG Register Map644
Table 114. IWDG Register Map and Reset Values644
System Window Watchdog (WWDG)645
Introduction645
WWDG Main Features645
WWDG Functional Description645
WWDG Block Diagram646
Enabling the Watchdog646
Controlling the Down-Counter646
How to Program the Watchdog Timeout646
Figure 208. Watchdog Block Diagram646
Figure 209. Window Watchdog Timing Diagram647
Debug Mode648
WWDG Interrupts648
WWDG Registers648
WWDG Control Register (WWDG_CR)648
WWDG Configuration Register (WWDG_CFR)649
WWDG Status Register (WWDG_SR)649
WWDG Register Map650
Table 115. WWDG Register Map and Reset Values650
Real-Time Clock (RTC)651
Introduction651
RTC Main Features652
RTC Implementation652
Table 116. RTC Implementation652
RTC Functional Description653
RTC Block Diagram653
Figure 210. RTC Block Diagram653
Table 117. RTC Pin PC13 Configuration654
Table 118. RTC_OUT Mapping655
Table 119. Effect of Low-Power Modes on RTC668
Table 120. Interrupt Control Bits668
RTC Control Register (RTC_CR)671
RTC Initialization and Status Register (RTC_ISR)674
RTC Prescaler Register (RTC_PRER)677
RTC Wakeup Timer Register (RTC_WUTR)678
RTC Alarm a Register (RTC_ALRMAR)679
RTC Alarm B Register (RTC_ALRMBR)680
RTC Write Protection Register (RTC_WPR)681
RTC Sub Second Register (RTC_SSR)681
RTC Shift Control Register (RTC_SHIFTR)682
RTC Timestamp Time Register (RTC_TSTR)683
RTC Timestamp Date Register (RTC_TSDR)684
RTC Time-Stamp Sub Second Register (RTC_TSSSR)685
RTC Calibration Register (RTC_CALR)686
RTC Tamper Configuration Register (RTC_TAMPCR)687
RTC Alarm a Sub Second Register (RTC_ALRMASSR)690
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)691
RTC Option Register (RTC_OR)692
RTC Backup Registers (Rtc_Bkpxr)692
RTC Register Map693
Table 121. RTC Register Map and Reset Values693
Inter-Integrated Circuit (I2C) Interface695
Introduction695
I2C Main Features695
I2C Implementation696
I2C Functional Description696
Table 122. Stm32L0X3 I2C Features696
I2C1/3 Block Diagram697
Figure 211. I2C1/3 Block Diagram697
I2C2 Block Diagram698
Figure 212. I2C2 Block Diagram698
I2C Pins and Internal Signals699
I2C Clock Requirements699
Mode Selection699
Table 123. I2C Input/Output Pins699
Table 124. I2C Internal Input/Output Signals699
Communication Flow700
I2C Initialization700
Enabling and Disabling the Peripheral700
Noise Filters700
Figure 213. I2C Bus Protocol700
Table 125. Comparison of Analog Vs. Digital Filters701
I2C Timings702
Figure 214. Setup and Hold Timings702
Software Reset705
Figure 215. I2C Initialization Flowchart705
Data Transfer706
Figure 216. Data Reception706
Figure 217. Data Transmission707
Table 127. I2C Configuration708
Figure 218. Slave Initialization Flowchart710
Figure 219. Transfer Sequence Flowchart for I2C Slave Transmitter712
Nostretch= 0712
Figure 220. Transfer Sequence Flowchart for I2C Slave Transmitter713
Nostretch= 1713
Figure 221. Transfer Bus Diagrams for I2C Slave Transmitter714
Figure 222. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0715
Figure 223. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1716
Figure 224. Transfer Bus Diagrams for I2C Slave Receiver716
Figure 225. Master Clock Generation718
Table 128. I2C-Smbus Specification Clock Timings719
Figure 226. Master Initialization Flowchart720
Figure 227. 10-Bit Address Read Access with HEAD10R=0720
Figure 228. 10-Bit Address Read Access with HEAD10R=1721
Figure 229. Transfer Sequence Flowchart for I2C Master Transmitter for N≤255 Bytes722
Figure 230. Transfer Sequence Flowchart for I2C Master Transmitter for N>255 Bytes723
Figure 231. Transfer Bus Diagrams for I2C Master Transmitter724
Figure 232. Transfer Sequence Flowchart for I2C Master Receiver for N≤255 Bytes726
Figure 233. Transfer Sequence Flowchart for I2C Master Receiver for N >255 Bytes727
Figure 234. Transfer Bus Diagrams for I2C Master Receiver728
Table 129. Examples of Timing Settings for Fi2Cclk = 8 Mhz729
Table 130. Examples of Timings Settings for Fi2Cclk = 16 Mhz729
Table 131. Smbus Timeout Specifications731
Figure 235. Timeout Intervals for T732
LOW:SEXT , T LOW:MEXT732
Table 132. Smbus with PEC Configuration734
Table 133. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies735
(Max T IDLE = 50 Μs)735
Figure 236. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC736
Figure 237. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)737
Figure 238. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC738
Figure 239. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)739
Figure 240. Bus Transfer Diagrams for Smbus Master Transmitter740
Figure 241. Bus Transfer Diagrams for Smbus Master Receiver742
Table 136. Effect of Low-Power Modes on the I2C746
Table 137. I2C Interrupt Requests747
Table 138. I2C Register Map and Reset Values762
Table 139. Stm32L0X3 USART/LPUART Features766
Figure 242. USART Block Diagram768
Figure 243. Word Length Programming770
Figure 244. Configurable Stop Bits772
Figure 245. TC/TXE Behavior When Transmitting773
Figure 246. Start Bit Detection When Oversampling by 16 or 8774
Figure 247. Data Sampling When Oversampling by 16777
Table 140. Noise Detection from Sampled Data778
Figure 248. Data Sampling When Oversampling by 8778
Table 141. Error Calculation for Programmed Baud Rates at F781
Oversampling by 16 or by 8781
Table 142. Tolerance of the USART Receiver When BRR [3:0] = 0000782
Table 143. Tolerance of the USART Receiver When BRR [3:0] Is Different from 0000782
Figure 249. Mute Mode Using Idle Line Detection785
Figure 250. Mute Mode Using Address Mark Detection786
Table 144. Frame Formats787
Figure 251. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)789
Figure 252. Break Detection in LIN Mode Vs. Framing Error Detection790
Figure 253. USART Example of Synchronous Transmission791
Figure 254. USART Data Clock Timing Diagram (M Bits = 00)791
Figure 255. USART Data Clock Timing Diagram (M Bits = 01)792
Figure 256. RX Data Setup/Hold Time792
Figure 257. ISO 7816-3 Asynchronous Protocol794
Figure 258. Parity Error Detection Using the 1.5 Stop Bits795
Figure 259. Irda SIR ENDEC- Block Diagram799
Figure 260. Irda Data Modulation (3/16) -Normal Mode800
Figure 261. Transmission Using DMA801
Figure 262. Reception Using DMA802
Figure 263. Hardware Flow Control between 2 Usarts802
Figure 264. RS232 RTS Flow Control803
Figure 265. RS232 CTS Flow Control804
Table 145. Effect of Low-Power Modes on the USART806
Table 146. USART Interrupt Requests806
Figure 266. USART Interrupt Mapping Diagram807
Table 147. USART Register Map and Reset Values829
Table 148. Stm32L0X3 USART/LPUART Features833
Figure 267. LPUART Block Diagram834
Figure 268. Word Length Programming836
Figure 269. Configurable Stop Bits837
Figure 270. TC/TXE Behavior When Transmitting839
Table 149. Error Calculation for Programmed Baud Rates at Fck = 32.768 Khz843
Table 150. Error Calculation for Programmed Baud Rates at Fck = 32 Mhz843
Table 151. Tolerance of the LPUART Receiver844
Figure 271. Mute Mode Using Idle Line Detection846
Table 152. Frame Formats847
Figure 272. Mute Mode Using Address Mark Detection847
Figure 273. Transmission Using DMA850
Figure 274. Reception Using DMA851
Figure 275. Hardware Flow Control between 2 Lpuarts851
Figure 276. RS232 RTS Flow Control852
Figure 277. RS232 CTS Flow Control853
Table 153. Effect of Low-Power Modes on the LPUART856
Table 154. LPUART Interrupt Requests856
Figure 278. LPUART Interrupt Mapping Diagram857
Table 155. LPUART Register Map and Reset Values872
Table 156. Stm32L0X3 SPI Implementation874
Figure 279. SPI Block Diagram875
Figure 280. Full-Duplex Single Master/ Single Slave Application876
Figure 281. Half-Duplex Single Master/ Single Slave Application877
Figure 282. Simplex Single Master/Single Slave Application878
Slave in Receive-Only Mode)878
Figure 283. Master and Three Independent Slaves879
Figure 284. Multi-Master Application880
Figure 285. Hardware/Software Slave Select Management881
Figure 286. Data Clock Timing Diagram883
Figure 287. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers886
Figure 288. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers887
Figure 289. Transmission Using DMA889
Figure 290. Reception Using DMA890
Figure 291. TI Mode Transfer893
Table 157. SPI Interrupt Requests895
Figure 292. I896
Figure 293. Full-Duplex Communication898
Figure 294. I S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)899
Figure 295. I S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)899
Figure 296. Transmitting 0X8Eaa33900
Figure 297. Receiving 0X8Eaa33900
Figure 298. I900
Figure 299. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame901
Figure 300. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0901
Figure 301. MSB Justified 24-Bit Frame Length with CPOL = 0901
Figure 302. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0902
Figure 303. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0902
Figure 304. LSB Justified 24-Bit Frame Length with CPOL = 0902
Figure 305. Operations Required to Transmit 0X3478Ae903
Figure 306. Operations Required to Receive 0X3478Ae903
Figure 307. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0903
Figure 308. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame904
Figure 309. PCM Standard Waveforms (16-Bit)904
Figure 310. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)904
Figure 311. Audio Sampling Frequency Definition905
Figure 312. I905
Table 158. Audio-Frequency Precision Using Standard 8 Mhz HSE906
Table 159. I912
Table 160. SPI Register Map and Reset Values922
Table 161. Stm32L0X3 USB Implementation923
Figure 313. USB Peripheral Block Diagram924
Figure 314. Packet Buffer Areas with Examples of Buffer Description Table Locations928
Table 162. Double-Buffering Buffer Flag Definition933
Table 163. Bulk Double-Buffering Memory Buffers Usage933
Table 164. Isochronous Memory Buffers Usage935
Table 165. Resume Event Detection936
Table 166. Reception Status Encoding949
Table 167. Endpoint Type Encoding949
Table 168. Endpoint Kind Meaning949
Table 169. Transmission Status Encoding950
Table 170. Definition of Allocated Buffer Memory953
Table 171. USB Register Map and Reset Values954
Figure 315. Block Diagram of Stm32L0X3 MCU and Cortex956
Table 172. SW Debug Port Pins957
Table 174. Packet Request (8-Bits)959
Table 175. ACK Response (3 Bits)960
Table 176. DATA Transfer (33 Bits)960
Table 177. SW-DP Registers961
Table 178. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]962
Table 179. Core Debug Registers963
Table 180. DBG Register Map and Reset Values970
Table 181. Document Revision History1021

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