ST STM32L0x3 User Manual

Reset and clock control (RCC) RM0367
212/1043 RM0367 Rev 7
7.3.16 GPIO clock enable in Sleep mode register (RCC_IOPSMENR)
Address: 0x3C
Reset value: the bits corresponding to the available GPIO ports are set
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res.
IOPHS
MEN
Res. Res.
IOPES
MEN
IOPDS
MEN
IOPCS
MEN
IOPBS
MEN
IOPAS
MEN
rw rw rw rw rw rw
Bits 31: 8 Reserved, must be kept at reset value.
Bit 7 IOPHSMEN: Port H clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port H clock is disabled in Sleep mode
1: Port H clock is enabled in Sleep mode (if enabled by IOPHEN)
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 IOPESMEN: Port E clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port E clock is disabled in Sleep mode
1: Port E clock is enabled in Sleep mode (if enabled by IOPDEN)
Bit 3 IOPDSMEN: Port D clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port D clock is disabled in Sleep mode
1: Port D clock is enabled in Sleep mode (if enabled by IOPDEN)
Bit 2 IOPCSMEN: Port C clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port C clock is disabled in Sleep mode
1: Port C clock is enabled in Sleep mode (if enabled by IOPCEN)
Bit 1 IOPBSMEN: Port B clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port B clock is disabled in Sleep mode
1: Port B clock is enabled in Sleep mode (if enabled by IOPBEN)
Bit 0 IOPASMEN: Port A clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port A clock is disabled in Sleep mode
1: Port A clock is enabled in Sleep mode (if enabled by IOPAEN)

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English